[Xen-ia64-devel] [patch 04/12] ia64: Add identity mapping of EFI memory to alt_dtlb_miss

[Simon Horman <horms@xxxxxxxxxxxx>]

Cc: Isaku Yamahata <yamahata@xxxxxxxxxxxxx>
Cc: Tristan Gingold <tgingold@xxxxxxx>
Cc: Alex Williamson <alex.williamson@xxxxxx>
Cc: Aron Griffis <aron@xxxxxx>
Signed-off-by: Simon Horman <horms@xxxxxxxxxxxx>

Index: 20071119-ia64/xen/arch/ia64/xen/ivt.S
===================================================================
--- 20071119-ia64.orig/xen/arch/ia64/xen/ivt.S  2007-11-25 21:36:30.000000000 
-0700
+++ 20071119-ia64/xen/arch/ia64/xen/ivt.S       2007-11-25 21:44:46.000000000 
-0700
@@ -207,17 +207,39 @@
 (p8)   br.cond.sptk frametable_miss ;;
 #endif
        // If it is not a Xen address, handle it via page_fault.
+       // If it is not a Xen address, handle it via page_fault.
+       //    !( ((r22 == 0x18 || r22 == 0x1c) && rr[6] == XEN_EFI_RID) ||
+       //       r22 == 0x1e )
+       // Note that rr[6] == XEN_EFI_RID implies rr[7] == XEN_EFI_RID
        extr.u r22=r16,59,5
        ;;
        dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN   // clear the key
-       cmp.ne p8,p0=0x1e,r22
-(p8)   br.cond.sptk page_fault
+       mov r23=6
+       ;;
+       mov r23=rr[r23]
+       ;;
+       mov r25=XEN_EFI_RID
+       cmp.eq p8,p0=0x18,r22           // 0xc...
+       ;;
+       cmp.eq.or p8,p0=0x1c,r22        // 0xe...
+       ;;
+       cmp.eq.and p8,p0=r25,r23        // rr[6] == XEN_EFI_RID
        ;;
+       cmp.eq.or p8,p0=0x1e,r22        // 0xf...
+       ;;
+(p8)   br.cond.spnt alt_dtlb_miss_identity_map
+       br.cond.spnt page_fault
+       ;;
+alt_dtlb_miss_identity_map:
        dep r21=-1,r21,IA64_PSR_ED_BIT,1
        or r19=r19,r17          // insert PTE control bits into r19
        mov cr.itir=r20         // set itir with cleared key
        ;;
-       dep r19=r18,r19,4,1     // set bit 4 (uncached) if access to UC area
+       cmp.ne p8,p0=r0,r18             // Xen UC bit set
+       ;;
+       cmp.eq.or p8,p0=0x18,r22        // Region 6 is UC for EFI
+       ;;
+(p8)   dep r19=-1,r19,4,1      // set bit 4 (uncached) if access to UC area
 (p6)   mov cr.ipsr=r21
        ;;
 (p7)   itc.d r19               // insert the TLB entry

-- 

-- 
Horms


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