Re: [Xen-merge] write_cr{0,4}

[Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>]

On 27 Dec 2005, at 18:48, Kurt Garloff wrote:

> On Fri, Dec 23, 2005 at 11:39:45AM +0000, Keir Fraser wrote:
> > Writes to cr0 already are emulated -- the TS bit is virtualised and 
> > all
> > other modified bits are ignored. We could also emulate (ignore) writes
> > to cr4, if that avoids xen-specific changes in the guest. The change 
> > to
> > do this is utterly trivial. Reads of cr4 are already emulated.
> Hmm, the nVidia folks use CR4 to enable PAT ...
> Is this something we want to support in dom0 ?
PAT is always enabled, on processors that support it. There's no enable 
flag in CR4. The PAT MSRs have to be rewritten to provide a type code 
for write-combining, however, and we'll need to virtualize and/or 
pass-through those writes for domain0 (or other suitably privileged 
domain) in future.
> On the long term, I hope we'll have PAT replace MTRR in dom0
> even without nVidia ...
'Enabling use of PAT' isn't that hard -- usually that just means 
provide a mapping for write-combining memory type. If we allow PAT 
codes to be used by other than domain0, however, then we'll want to be 
sure we don't allow aliased types (e.g., a page that is mapped both 
cacheable and write-combining, in two different places). That kind of 
thing can lead to system lockups.
 -- Keir


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