Re: [Xen-users] Enabling Xen on HiSilicon HIP05 board

[Ian Campbell <ian.campbell@xxxxxxxxxx>]

On Fri, 2015-07-17 at 09:38 +0000, Shameerali Kolothum Thodi wrote:
> Also please find attached the latest crash dump I am seeing. Please let me 
> know if this gives you any hints.

It's not one I've seen before I'm afraid.

> (XEN) CPU 15 booted.
> (XEN) Brought up 16 CPUs
> (XEN) P2M: 44-bit IPA with 44-bit PA
> (XEN) P2M: 4 levels with order-0 root, VTCR 0x80043594
> (XEN) I/O virtualisation disabled
> (XEN) *** LOADING DOMAIN 0 ***
> (XEN) Loading kernel from boot module @ 0000000007000000
> (XEN) Allocating 1:1 mappings totalling 128MB for dom0:
> (XEN) BANK[0] 0x00000008000000-0x00000010000000 (128MB)
> (XEN) Loading zImage from 0000000007000000 to 
> 0000000008080000-0000000008980000
> (XEN) Allocating PPI 16 for event channel interrupt
> (XEN) Loading dom0 DTB to 0x000000000fe00000-0x000000000fe01ea5
> (XEN) Scrubbing Free RAM on 1 nodes using 16 CPUs
> (XEN) .done.
> (XEN) Initial low memory virq threshold set at 0x4000 pages.
> (XEN) Std. Loglevel: All
> (XEN) Guest Loglevel: All
> (XEN) *** Serial input -> DOM0 (type 'CTRL-a' three times to switch input to 
> Xen)
> (XEN) Freed 264kB init memory.
> (XEN) d0v0: vGICD: RAZ on reserved register offset 0x00000c
> (XEN) d0v0: vGICR: write r2 offset 0x000180
> (XEN)  not found

These two seem to come from xen/arch/arm/vgic-v3.c

Neither GICD+0xc nor GICR+0x180 seem to be registers defined in my
version of the spec. This all might plausibly be related to the use of a
v4 rather than v3 gic?

> <G><3>

These are because the formatting of the previous message is a bit mad.

> traps.c:2417:d0v0 HSR=0x93820046 pc=0xffffffc000322bfc gva=0xffffff8000090180 
> gpa=0x0000008d110180

This trap will correspond to the unhandled write to vGICR+0x180, being
injected back to the guest as a trap since we didn't know what else to
do with it.

> (XEN) *** Serial input -> Xen (type 'CTRL-a' three times to switch input to 
> DOM0)
> (XEN) 'd' pressed -> dumping registers
> (XEN)
> (XEN) *** Dumping CPU0 guest state (d0v0): ***
> (XEN) ----[ Xen-4.6-unstable  arm64  debug=y  Not tainted ]----
> (XEN) CPU:    0
> (XEN) PC:     ffffffc0002ff830
> (XEN) LR:     ffffffc0002ff868
> (XEN) SP_EL0: 0000000000000000
> (XEN) SP_EL1: ffffffc00087fa80
> (XEN) CPSR:   80000145 MODE:64-bit EL1h (Guest Kernel, handler)
> (XEN)      X0: 0000000000000199  X1: 000000000000000c  X2: 000000007ddbf62d
> (XEN)      X3: 0000000000000000  X4: 0000000000000000  X5: 0000000000000006
> (XEN)      X6: ffffffc0008eaa74  X7: 696b206f74206465  X8: 0000000000000064
> (XEN)      X9: 0000000000000000 X10: ffffffc0008ea000 X11: ffffffc00089a000
> (XEN)     X12: 0101010101010101 X13: 0000000000000000 X14: 0ffffffffffffffd
> (XEN)     X15: 0000000000000007 X16: 0000000000000001 X17: 000000000000000e
> (XEN)     X18: 0000000000000007 X19: 0000000000000031 X20: 00000000004da5bc
> (XEN)     X21: 00000000004da620 X22: ffffffc0008e7000 X23: 0000000000000000
> (XEN)     X24: ffffffc00088f4b0 X25: 0000000000000000 X26: 0000000000000000
> (XEN)     X27: ffffffc000901c88 X28: ffffffc001801700  FP: ffffffc00087fa80
> (XEN)
> (XEN)    ELR_EL1: ffffffc000322bfc
> (XEN)    ESR_EL1: 96000000
> (XEN)    FAR_EL1: ffffff8000090180
> (XEN)
> (XEN)  SCTLR_EL1: 04c5d91d
> (XEN)    TCR_EL1: 34b5193519
> (XEN)  TTBR0_EL1: 000000000ffff000
> (XEN)  TTBR1_EL1: 000000000891e000
> (XEN)



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