Re: [Xen-users] xhci_hcd intterrupt affinity in Dom0/DomU limited to single interrupt

[Ian Campbell <ian.campbell@xxxxxxxxxx>]

On Tue, 2015-09-01 at 13:56 +0000, Justin Acker wrote:
> Thanks Ian,
> 
> I appreciate the explanation. I believe the device drivers do support 
> multiple queues when run natively without the Dom0 loaded. The device in 
> question is the xhci_hcd driver for which I/O transfers seem to be slowed 
> when the Dom0 is loaded. The behavior seems to pass through to the DomU 
> if pass through is enabled. I found some similar threads, but most relate 
> to Ethernet controllers. I tried some of the x2apic and x2apic_phys dom0 
> kernel arguments, but none distributed the pirqs. Based on the reading 
> relating to IRQs for Xen, I think pinning the pirqs to cpu0 is done to 
> avoid an I/O storm. I tried IRQ balance and when configured/adjusted it 
> will balance individual pirqs, but not multiple interrupts. 
> 
> Is there a way to force or enable pirq delivery to a set of cpus as you 
> mentioned above or omit a single device from being a assigned a PIRQ so 
> that its interrupt can be distributed across all cpus? 

A PIRQ is the way an interrupt is exposed to a PV guest, without it there
would be no interrupt at all.

I'm afraid I'm out of my depth WRT how x86/MSIs and Xen x86/PV pirqs
interact, in particular WRT configuring which set of CPUs can have the IRQ
delivered.

If no one else chimes in soon I'd suggest taking this to the dev list, at
the very least someone who knows what they are talking about (i.e. other
than me) might be able to help.

Ian.


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