clk {
	u-boot,dm-pre-reloc;
	#clock-cells = <0x1>;
	compatible = "xlnx,zynqmp-clk";
	clocks = <0x58 0x59 0x5a 0x5b 0x5c>;
	clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
	linux,phandle = <0x3>;
	phandle = <0x3>;
};

xlnx_dpdma: dma@fd4c0000 {
	compatible = "xlnx,dpdma";
	status = "okay";
	xen,passthrough = <0x1>;
	reg = <0x0 0xfd4c0000 0x0 0x1000>;
	interrupts = <0x0 0x7a 0x4>;
	interrupt-parent = <0x4>;
	clock-names = "axi_clk";
	power-domains = <0x51>;
	dma-channels = <0x6>;
	#dma-cells = <0x1>;
	clocks = <0x3 0x14>;
	#stream-id-cells = <0x1>;
	iommus = <&smmu 0xce3>;
	linux,phandle = <0x54>;
	phandle = <0x54>;
};

zynqmp-display@fd4a0000 {
	compatible = "xlnx,zynqmp-dpsub-1.7";
	status = "okay";
	xen,passthrough = <0x1>;
	reg = <0x0 0xfd4a0000 0x0 0x1000 0x0 0xfd4aa000 0x0 0x1000 0x0 0xfd4ab000 0x0 0x1000 0x0 0xfd4ac000 0x0 0x1000>;
	reg-names = "dp", "blend", "av_buf", "aud";
	interrupts = <0x0 0x77 0x4>;
	interrupt-parent = <0x4>;
	clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
	power-domains = <0x51>;
	clocks = <0x52 0x3 0x11 0x3 0x10>;
	phy-names = "dp-phy0";
	phys = <0x53 0x5 0x0 0x3 0x19bfcc0>;
	xlnx,max-lanes = <0x1>;
};