[Xen-changelog] [xen-unstable] x86: Pass through ERMS CPUID feature for HVM and PV guests

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User Yang, Wei <wei.y.yang@xxxxxxxxx>
# Date 1308053598 -3600
# Node ID f4a47275aebf383cf565e0a265a56a8c1110d45e
# Parent  337520d94cba906e64dbd3089d65cda8cf97d1d0
x86: Pass through ERMS CPUID feature for HVM and PV guests

This patch exposes ERMS feature to HVM and PV guests.

The REP MOVSB/STOSB instruction can enhance fast strings attempts to
move as much of the data with larger size load/stores as possible.

Signed-off-by: Yang, Wei <wei.y.yang@xxxxxxxxx>
---


diff -r 337520d94cba -r f4a47275aebf tools/libxc/xc_cpufeature.h
--- a/tools/libxc/xc_cpufeature.h       Tue Jun 14 13:04:09 2011 +0100
+++ b/tools/libxc/xc_cpufeature.h       Tue Jun 14 13:13:18 2011 +0100
@@ -126,5 +126,6 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
 #define X86_FEATURE_FSGSBASE     0 /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_SMEP         7 /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_ERMS         9 /* Enhanced REP MOVSB/STOSB */
 
 #endif /* __LIBXC_CPUFEATURE_H */
diff -r 337520d94cba -r f4a47275aebf tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c        Tue Jun 14 13:04:09 2011 +0100
+++ b/tools/libxc/xc_cpuid_x86.c        Tue Jun 14 13:13:18 2011 +0100
@@ -355,7 +355,8 @@
 
     case 0x00000007: /* Intel-defined CPU features */
         if ( input[1] == 0 ) {
-            regs[1] &= bitmaskof(X86_FEATURE_SMEP);
+            regs[1] &= (bitmaskof(X86_FEATURE_SMEP) |
+                        bitmaskof(X86_FEATURE_ERMS));
         } else
             regs[1] = 0;
         regs[0] = regs[2] = regs[3] = 0;
@@ -478,7 +479,8 @@
 
     case 7:
         if ( input[1] == 0 )
-            regs[1] &= bitmaskof(X86_FEATURE_FSGSBASE);
+            regs[1] &= (bitmaskof(X86_FEATURE_FSGSBASE) |
+                        bitmaskof(X86_FEATURE_ERMS));
         else
             regs[1] = 0;
         regs[0] = regs[2] = regs[3] = 0;
diff -r 337520d94cba -r f4a47275aebf xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c      Tue Jun 14 13:04:09 2011 +0100
+++ b/xen/arch/x86/traps.c      Tue Jun 14 13:13:18 2011 +0100
@@ -815,7 +815,8 @@
         break;
     case 7:
         if ( regs->ecx == 0 )
-            b &= cpufeat_mask(X86_FEATURE_FSGSBASE);
+            b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) |
+                  cpufeat_mask(X86_FEATURE_ERMS));
         else
             b = 0;
         a = c = d = 0;
diff -r 337520d94cba -r f4a47275aebf xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h  Tue Jun 14 13:04:09 2011 +0100
+++ b/xen/include/asm-x86/cpufeature.h  Tue Jun 14 13:13:18 2011 +0100
@@ -145,6 +145,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
 #define X86_FEATURE_FSGSBASE   (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_SMEP       (7*32+ 7) /* Supervisor Mode Execution 
Protection */
+#define X86_FEATURE_ERMS       (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
 
 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)

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