[Xen-changelog] [xen staging] gic-vgic: Drop an excessive clear_lrs

[patchbot@xxxxxxx]

commit cca87128aab1820d269f7ebc6c169f27dafdbadd
Author:     Andrii Anisov <andrii_anisov@xxxxxxxx>
AuthorDate: Wed Dec 12 20:20:54 2018 +0200
Commit:     Julien Grall <julien.grall@xxxxxxx>
CommitDate: Fri Dec 14 15:25:21 2018 +0000

    gic-vgic: Drop an excessive clear_lrs
    
    This action is excessive because for an invalid LR there is no need
    to write another invalid value to a register. So we can skip it here,
    saving a peripheral register write.
    Keep clearing the LR for the DEBUG build. This would make dumped
    invalid LRs be zero. That is more obvious than picking state bits
    from a non-zero value.
    
    Signed-off-by: Andrii Anisov <andrii_anisov@xxxxxxxx>
    Reviewed-by: Julien Grall <julien.grall@xxxxxxx>
---
 xen/arch/arm/gic-vgic.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c
index 990399cf3f..48922f5595 100644
--- a/xen/arch/arm/gic-vgic.c
+++ b/xen/arch/arm/gic-vgic.c
@@ -216,7 +216,9 @@ static void gic_update_one_lr(struct vcpu *v, int i)
     }
     else
     {
+#ifndef NDEBUG
         gic_hw_ops->clear_lr(i);
+#endif
         clear_bit(i, &this_cpu(lr_mask));
 
         if ( p->desc != NULL )
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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