[Xen-changelog] [xen staging] x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure

[patchbot@xxxxxxx]

commit 4aedd96d8d237a0347d01f32d4ca7ece77784f9d
Author:     Pu Wen <puwen@xxxxxxxx>
AuthorDate: Thu Apr 4 21:46:23 2019 +0800
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Thu Jun 6 15:28:21 2019 +0100

    x86/cpu/mce: Add Hygon Dhyana support to the MCA infrastructure
    
    The machine check architecture for Hygon Dhyana CPU is similar to the
    AMD family 17h one. Add vendor checking for Hygon Dhyana to share the
    code path of AMD family 17h.
    
    Signed-off-by: Pu Wen <puwen@xxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
    [Rebase over 0cd074144cb "x86/cpu: Renumber X86_VENDOR_* to form a bitmap"]
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/cpu/common.c              | 2 +-
 xen/arch/x86/cpu/mcheck/amd_nonfatal.c | 4 ++--
 xen/arch/x86/cpu/mcheck/mce.c          | 5 +++--
 xen/arch/x86/cpu/mcheck/mce_amd.c      | 5 ++++-
 xen/arch/x86/cpu/mcheck/non-fatal.c    | 3 ++-
 xen/arch/x86/cpu/mcheck/vmce.c         | 2 ++
 6 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 31294927a1..4985a4a0ae 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -331,7 +331,7 @@ void __init early_cpu_init(void)
                        hap_paddr_bits = PADDR_BITS;
        }
 
-       if (c->x86_vendor != X86_VENDOR_AMD)
+       if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)))
                park_offline_cpus = opt_mce;
 
        initialize_cpu_data(0);
diff --git a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c 
b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
index 222f539b1e..6e8901530a 100644
--- a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
+++ b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
@@ -203,10 +203,10 @@ static void mce_amd_work_fn(void *data)
 
 void __init amd_nonfatal_mcheck_init(struct cpuinfo_x86 *c)
 {
-       if (c->x86_vendor != X86_VENDOR_AMD)
+       if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)))
                return;
 
-       /* Assume we are on K8 or newer AMD CPU here */
+       /* Assume we are on K8 or newer AMD or Hygon CPU here */
 
        /* The threshold bitfields in MSR_IA32_MC4_MISC has
         * been introduced along with the SVME feature bit. */
diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c
index 30cdb06401..2d700036e9 100644
--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -778,6 +778,7 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp)
     switch ( c->x86_vendor )
     {
     case X86_VENDOR_AMD:
+    case X86_VENDOR_HYGON:
         inited = amd_mcheck_init(c);
         break;
 
@@ -1172,10 +1173,10 @@ static bool x86_mc_msrinject_verify(struct 
xen_mc_msrinject *mci)
 
             /* MSRs that the HV will take care of */
             case MSR_K8_HWCR:
-                if ( c->x86_vendor == X86_VENDOR_AMD )
+                if ( c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
                     reason = "HV will operate HWCR";
                 else
-                    reason = "only supported on AMD";
+                    reason = "only supported on AMD or Hygon";
                 break;
 
             default:
diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c 
b/xen/arch/x86/cpu/mcheck/mce_amd.c
index ed29fcc312..9b2852cc7e 100644
--- a/xen/arch/x86/cpu/mcheck/mce_amd.c
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -286,7 +286,10 @@ enum mcheck_type
 amd_mcheck_init(struct cpuinfo_x86 *ci)
 {
     uint32_t i;
-    enum mcequirk_amd_flags quirkflag = mcequirk_lookup_amd_quirkdata(ci);
+    enum mcequirk_amd_flags quirkflag = 0;
+
+    if ( ci->x86_vendor != X86_VENDOR_HYGON )
+        quirkflag = mcequirk_lookup_amd_quirkdata(ci);
 
     /* Assume that machine check support is available.
      * The minimum provided support is at least the K8. */
diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c 
b/xen/arch/x86/cpu/mcheck/non-fatal.c
index d12e8f23ba..77be4185e4 100644
--- a/xen/arch/x86/cpu/mcheck/non-fatal.c
+++ b/xen/arch/x86/cpu/mcheck/non-fatal.c
@@ -101,7 +101,8 @@ static int __init init_nonfatal_mce_checker(void)
         */
        switch (c->x86_vendor) {
        case X86_VENDOR_AMD:
-               /* Assume we are on K8 or newer AMD CPU here */
+       case X86_VENDOR_HYGON:
+               /* Assume we are on K8 or newer AMD or Hygon CPU here */
                amd_nonfatal_mcheck_init(c);
                break;
 
diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index f15835e9f6..4f5de07e01 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -154,6 +154,7 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t 
msr, uint64_t *val)
             break;
 
         case X86_VENDOR_AMD:
+        case X86_VENDOR_HYGON:
             ret = vmce_amd_rdmsr(v, msr, val);
             break;
 
@@ -284,6 +285,7 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, 
uint64_t val)
             break;
 
         case X86_VENDOR_AMD:
+        case X86_VENDOR_HYGON:
             ret = vmce_amd_wrmsr(v, msr, val);
             break;
 
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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