[Xen-changelog] [xen staging] x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery

[patchbot@xxxxxxx]

commit 5b516f02921391dd6c4737aef1c10a540af100d1
Author:     Pu Wen <puwen@xxxxxxxx>
AuthorDate: Thu Apr 4 21:46:33 2019 +0800
Commit:     Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
CommitDate: Thu Jun 6 15:28:21 2019 +0100

    x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery
    
    The Hygon Dhyana CPU has the same speculative execution as AMD family
    17h, so share AMD Retpoline and PTI mitigation code with Hygon Dhyana.
    
    Signed-off-by: Pu Wen <puwen@xxxxxxxx>
    Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
    [Rebase over 0cd074144cb "x86/cpu: Renumber X86_VENDOR_* to form a bitmap"]
    Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/spec_ctrl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index e66879f5c0..cada9a058e 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -192,7 +192,7 @@ int8_t __read_mostly opt_xpti_domu = -1;
 
 static __init void xpti_init_default(uint64_t caps)
 {
-    if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+    if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
         caps = ARCH_CAPS_RDCL_NO;
 
     if ( caps & ARCH_CAPS_RDCL_NO )
@@ -438,7 +438,7 @@ static bool __init retpoline_safe(uint64_t caps)
 {
     unsigned int ucode_rev = this_cpu(ucode_cpu_info).cpu_sig.rev;
 
-    if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+    if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
         return true;
 
     if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
--
generated by git-patchbot for /home/xen/git/xen.git#staging

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