[qemu-xen staging] target/riscv: Fix pmp NA4 implementation

[patchbot@xxxxxxx]

commit cfad709bceb629a4ebeb5d8a3acd1871b9a6436b
Author:     Alexandre Mergnat <amergnat@xxxxxxxxxxxx>
AuthorDate: Mon Jul 6 10:45:50 2020 +0200
Commit:     Alistair Francis <alistair.francis@xxxxxxx>
CommitDate: Mon Jul 13 17:25:37 2020 -0700

    target/riscv: Fix pmp NA4 implementation
    
    The end address calculation for NA4 mode is wrong because the address
    used isn't shifted.
    
    It doesn't watch 4 bytes but a huge range because the end address
    calculation is wrong.
    
    The solution is to use the shifted address calculated for start address
    variable.
    
    Modifications are tested on Zephyr OS userspace test suite which works
    for other RISC-V boards (E31 and E34 core).
    
    Signed-off-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx>
    Reviewed-by: Alistair Francis <alistair.francis@xxxxxxx>
    Message-id: 20200706084550.24117-1-amergnat@xxxxxxxxxxxx
    Message-Id: <20200706084550.24117-1-amergnat@xxxxxxxxxxxx>
    [ Changes by AF:
     - Improve the commit title and message
    ]
    Signed-off-by: Alistair Francis <alistair.francis@xxxxxxx>
---
 target/riscv/pmp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9418660f1b..2a2b9f5363 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -171,7 +171,7 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t 
pmp_index)
 
     case PMP_AMATCH_NA4:
         sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
-        ea = (this_addr + 4u) - 1u;
+        ea = (sa + 4u) - 1u;
         break;
 
     case PMP_AMATCH_NAPOT:
--
generated by git-patchbot for /home/xen/git/qemu-xen.git#staging