[qemu-xen staging] Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200713' into staging

[patchbot@xxxxxxx]

commit aeb07b5f6e69ce93afea71027325e3e7a22d2149
Merge: beff47a2f6a8295161f98a9dac94e18e5376e749 
cfad709bceb629a4ebeb5d8a3acd1871b9a6436b
Author:     Peter Maydell <peter.maydell@xxxxxxxxxx>
AuthorDate: Tue Jul 14 17:58:00 2020 +0100
Commit:     Peter Maydell <peter.maydell@xxxxxxxxxx>
CommitDate: Tue Jul 14 17:58:00 2020 +0100

    Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20200713' into staging
    
    This is a colection of bug fixes and small imrprovements for RISC-V.
    
    This includes some vector extensions fixes, a PMP bug fix, OpenTitan
    UART bug fix and support for OpenSBI dynamic firmware.
    
    # gpg: Signature made Tue 14 Jul 2020 01:29:44 BST
    # gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
    # gpg: Good signature from "Alistair Francis <alistair@xxxxxxxxxxxxx>" 
[full]
    # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 
7054
    
    * remotes/alistair/tags/pull-riscv-to-apply-20200713:
      target/riscv: Fix pmp NA4 implementation
      tcg/riscv: Remove superfluous breaks
      hw/char: Convert the Ibex UART to use the registerfields API
      hw/char: Convert the Ibex UART to use the qdev Clock model
      target/riscv: fix vill bit index in vtype register
      target/riscv: fix return value of do_opivx_widen()
      target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
      target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
      hw/riscv: Modify MROM size to end at 0x10000
      RISC-V: Support 64 bit start address
      riscv: Add opensbi firmware dynamic support
      RISC-V: Copy the fdt in dram instead of ROM
      riscv: Unify Qemu's reset vector code path
      hw/riscv: virt: Sort the SoC memmap table entries
      MAINTAINERS: Add an entry for OpenSBI firmware
    
    Signed-off-by: Peter Maydell <peter.maydell@xxxxxxxxxx>

 MAINTAINERS                             |   7 ++
 hw/char/ibex_uart.c                     | 158 ++++++++++++++++++--------------
 hw/riscv/boot.c                         | 107 +++++++++++++++++++++
 hw/riscv/sifive_u.c                     |  53 ++++++-----
 hw/riscv/spike.c                        |  59 ++++--------
 hw/riscv/virt.c                         |  63 ++++---------
 include/hw/char/ibex_uart.h             |  79 ++++++++--------
 include/hw/riscv/boot.h                 |   7 ++
 include/hw/riscv/boot_opensbi.h         |  58 ++++++++++++
 target/riscv/cpu.h                      |   2 +-
 target/riscv/insn_trans/trans_rvv.inc.c |   9 +-
 target/riscv/pmp.c                      |   2 +-
 tcg/riscv/tcg-target.inc.c              |   2 -
 13 files changed, 387 insertions(+), 219 deletions(-)
--
generated by git-patchbot for /home/xen/git/qemu-xen.git#staging