[qemu-xen staging] hw/riscv: sifive_e: Correct debug block size

[patchbot@xxxxxxx]

commit e79d27cb322b60b460b709d2c74ff7d77cde0565
Author:     Bin Meng <bmeng.cn@xxxxxxxxx>
AuthorDate: Thu Jul 16 02:30:56 2020 -0700
Commit:     Alistair Francis <alistair.francis@xxxxxxx>
CommitDate: Wed Jul 22 09:39:46 2020 -0700

    hw/riscv: sifive_e: Correct debug block size
    
    Currently the debug region size is set to 0x100, but according to
    FE310-G000 and FE310-G002 manuals:
    
      FE310-G000: 0x100 - 0xFFF
      FE310-G002: 0x0   - 0xFFF
    
    Change the size to 0x1000 that applies to both.
    
    Signed-off-by: Bin Meng <bmeng.cn@xxxxxxxxx>
    Reviewed-by: Alistair Francis <alistair.francis@xxxxxxx>
    Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@xxxxxxxxx>
    Signed-off-by: Alistair Francis <alistair.francis@xxxxxxx>
---
 hw/riscv/sifive_e.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 7bb97b463d..c8b060486a 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -54,7 +54,7 @@ static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
 } sifive_e_memmap[] = {
-    [SIFIVE_E_DEBUG] =    {        0x0,      0x100 },
+    [SIFIVE_E_DEBUG] =    {        0x0,     0x1000 },
     [SIFIVE_E_MROM] =     {     0x1000,     0x2000 },
     [SIFIVE_E_OTP] =      {    0x20000,     0x2000 },
     [SIFIVE_E_CLINT] =    {  0x2000000,    0x10000 },
--
generated by git-patchbot for /home/xen/git/qemu-xen.git#staging