[qemu-xen staging] target/riscv: Fix the range of pmpcfg of CSR funcion table

[patchbot@xxxxxxx]

commit 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d
Author:     Zong Li <zong.li@xxxxxxxxxx>
AuthorDate: Tue Jul 21 20:40:50 2020 +0800
Commit:     Alistair Francis <alistair.francis@xxxxxxx>
CommitDate: Wed Jul 22 09:41:36 2020 -0700

    target/riscv: Fix the range of pmpcfg of CSR funcion table
    
    The range of Physical Memory Protection should be from CSR_PMPCFG0
    to CSR_PMPCFG3, not to CSR_PMPADDR9.
    
    Signed-off-by: Zong Li <zong.li@xxxxxxxxxx>
    Reviewed-by: Alistair Francis <alistair.francis@xxxxxxx>
    Reviewed-by: Bin Meng <bin.meng@xxxxxxxxxxxxx>
    Message-Id: 
<eae49e9252c9596e4f3bdb471772f79235141a87.1595335112.git.zong.li@xxxxxxxxxx>
    Signed-off-by: Alistair Francis <alistair.francis@xxxxxxx>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ac01c835e1..6a96a01b1c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1353,7 +1353,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTINST] =              { hmode,   read_mtinst,      write_mtinst     
},
 
     /* Physical Memory Protection */
-    [CSR_PMPCFG0  ... CSR_PMPADDR9] =  { pmp,   read_pmpcfg,  write_pmpcfg   },
+    [CSR_PMPCFG0  ... CSR_PMPCFG3]   = { pmp,   read_pmpcfg,  write_pmpcfg   },
     [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp,   read_pmpaddr, write_pmpaddr  },
 
     /* Performance Counters */
--
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