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[xen master] x86emul: support SHA512

Date: Tue, 16 Jan 2024 01:33:12 +0000

Delivery-date: Tue, 16 Jan 2024 01:33:13 +0000

List-id: "Change log for Mercurial \(receive only\)" <xen-changelog.lists.xenproject.org>

commit aa18530282cf65fd036a14224a1954afea7a567f Author: Jan Beulich <jbeulich@xxxxxxxx> AuthorDate: Mon Jan 15 12:10:40 2024 +0100 Commit: Jan Beulich <jbeulich@xxxxxxxx> CommitDate: Mon Jan 15 12:10:40 2024 +0100 x86emul: support SHA512 Since the insns here don't access memory, I didn't think it was necessary to extend our SHA test for them. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> --- tools/misc/xen-cpuid.c | 2 ++ tools/tests/x86_emulator/predicates.c | 3 +++ tools/tests/x86_emulator/x86-emulate.h | 1 + xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/x86_emulate/decode.c | 8 ++++++++ xen/arch/x86/x86_emulate/private.h | 1 + xen/arch/x86/x86_emulate/x86_emulate.c | 8 ++++++++ xen/include/public/arch-x86/cpufeatureset.h | 1 + xen/tools/gen-cpuid.py | 2 +- 9 files changed, 26 insertions(+), 1 deletion(-) diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 3598d37f93..3082cd52e6 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -185,6 +185,8 @@ static const char *const str_7d0[32] = static const char *const str_7a1[32] = { + [ 0] = "sha512", + [ 4] = "avx-vnni", [ 5] = "avx512-bf16", [10] = "fzrm", [11] = "fsrs", diff --git a/tools/tests/x86_emulator/predicates.c b/tools/tests/x86_emulator/predicates.c index b4d9b7836f..0072889a8c 100644 --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1396,6 +1396,9 @@ static const struct vex { { { 0xbd }, 2, T, R, pfx_66, Wn, LIG }, /* vnmadd231s{s,d} */ { { 0xbe }, 2, T, R, pfx_66, Wn, Ln }, /* vnmsub231p{s,d} */ { { 0xbf }, 2, T, R, pfx_66, Wn, LIG }, /* vnmsub231s{s,d} */ + { { 0xcb, 0xc0 }, 2, F, N, pfx_f2, W0, L1 }, /* vsha512rnds2 */ + { { 0xcc, 0xc0 }, 2, F, N, pfx_f2, W0, L1 }, /* vsha512msg1 */ + { { 0xcd, 0xc0 }, 2, F, N, pfx_f2, W0, L1 }, /* vsha512msg2 */ { { 0xcf }, 2, T, R, pfx_66, W0, Ln }, /* vgf2p8mulb */ { { 0xd2 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpwuud */ { { 0xd2 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwusd */ diff --git a/tools/tests/x86_emulator/x86-emulate.h b/tools/tests/x86_emulator/x86-emulate.h index 4434d6c243..7d5d1ce700 100644 --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -176,6 +176,7 @@ void wrpkru(unsigned int val); #define cpu_has_avx512_vp2intersect (cp.feat.avx512_vp2intersect && xcr0_mask(0xe6)) #define cpu_has_serialize cp.feat.serialize #define cpu_has_avx512_fp16 (cp.feat.avx512_fp16 && xcr0_mask(0xe6)) +#define cpu_has_sha512 (cp.feat.sha512 && xcr0_mask(6)) #define cpu_has_avx_vnni (cp.feat.avx_vnni && xcr0_mask(6)) #define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6)) #define cpu_has_avx_ifma (cp.feat.avx_ifma && xcr0_mask(6)) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 3e89a6f007..81cb14faba 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -184,6 +184,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_arch_caps boot_cpu_has(X86_FEATURE_ARCH_CAPS) /* CPUID level 0x00000007:1.eax */ +#define cpu_has_sha512 boot_cpu_has(X86_FEATURE_SHA512) #define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI) #define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16) #define cpu_has_avx_ifma boot_cpu_has(X86_FEATURE_AVX_IFMA) diff --git a/xen/arch/x86/x86_emulate/decode.c b/xen/arch/x86/x86_emulate/decode.c index c85d98c04a..29b35a6d14 100644 --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -916,6 +916,14 @@ decode_0f38(struct x86_emulate_state *s, case X86EMUL_OPC_EVEX_66(0, 0x7c): /* vpbroadcast{d,q} */ break; + case X86EMUL_OPC_VEX_F2(0, 0xcc): /* vsha512msg1 */ + case X86EMUL_OPC_VEX_F2(0, 0xcd): /* vsha512msg2 */ + s->desc |= TwoOp; + /* fallthrough */ + case X86EMUL_OPC_VEX_F2(0, 0xcb): /* vsha512rnds2 */ + s->simd_size = simd_other; + break; + case 0xf0: /* movbe / crc32 */ s->desc |= s->vex.pfx == vex_f2 ? ByteOp : Mov; if ( s->vex.pfx >= vex_f3 ) diff --git a/xen/arch/x86/x86_emulate/private.h b/xen/arch/x86/x86_emulate/private.h index 3552f3277f..126c0ac5a6 100644 --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -587,6 +587,7 @@ amd_like(const struct x86_emulate_ctxt *ctxt) #define vcpu_has_serialize() (ctxt->cpuid->feat.serialize) #define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk) #define vcpu_has_avx512_fp16() (ctxt->cpuid->feat.avx512_fp16) +#define vcpu_has_sha512() (ctxt->cpuid->feat.sha512) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c index 92e7e622bc..af519f36bb 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6872,6 +6872,14 @@ x86_emulate( host_and_vcpu_must_have(avx512er); goto simd_zmm_scalar_sae; + case X86EMUL_OPC_VEX_F2(0x0f38, 0xcb): /* vsha512rnds2 xmm,ymm,ymm */ + case X86EMUL_OPC_VEX_F2(0x0f38, 0xcc): /* vsha512msg1 xmm,ymm */ + case X86EMUL_OPC_VEX_F2(0x0f38, 0xcd): /* vsha512msg2 ymm,ymm */ + host_and_vcpu_must_have(sha512); + generate_exception_if(ea.type != OP_REG || vex.w || !vex.l, X86_EXC_UD); + op_bytes = 32; + goto simd_0f_ymm; + case X86EMUL_OPC_66(0x0f38, 0xcf): /* gf2p8mulb xmm/m128,xmm */ host_and_vcpu_must_have(gfni); goto simd_0f38_common; diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index c2c977eb62..ad12e24d95 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -277,6 +277,7 @@ XEN_CPUFEATURE(CORE_CAPS, 9*32+30) /* IA32_CORE_CAPABILITIES MSR */ XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */ /* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */ +XEN_CPUFEATURE(SHA512, 10*32+ 0) /*A SHA512 Instructions */ XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */ XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */ XEN_CPUFEATURE(FZRM, 10*32+10) /*A Fast Zero-length REP MOVSB */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 2617c8f8b9..edd4838825 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -285,7 +285,7 @@ def crunch_numbers(state): # enabled. Certain later extensions, acting on 256-bit vectors of # integers, better depend on AVX2 than AVX. AVX2: [AVX512F, VAES, VPCLMULQDQ, AVX_VNNI, AVX_IFMA, AVX_VNNI_INT8, - AVX_VNNI_INT16], + AVX_VNNI_INT16, SHA512], # AVX512F is taken to mean hardware support for 512bit registers # (which in practice depends on the EVEX prefix to encode) as well -- generated by git-patchbot for /home/xen/git/xen.git#master

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