[xen staging] x86/HVM: correct partial HPET_STATUS write emulation

[patchbot@xxxxxxx]

commit 41d358d2f9607ba37c216effa39b9f1bc58de69d
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Thu Aug 29 10:02:20 2024 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Thu Aug 29 10:02:20 2024 +0200

    x86/HVM: correct partial HPET_STATUS write emulation
    
    For partial writes the non-written parts of registers are folded into
    the full 64-bit value from what they're presently set to. That's wrong
    to do though when the behavior is write-1-to-clear: Writes not
    including to low 3 bits would unconditionally clear all ISR bits which
    are presently set. Re-calculate the value to use.
    
    Fixes: be07023be115 ("x86/vhpet: add support for level triggered 
interrupts")
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
 xen/arch/x86/hvm/hpet.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/hvm/hpet.c b/xen/arch/x86/hvm/hpet.c
index 87642575f9..f0e5f877f4 100644
--- a/xen/arch/x86/hvm/hpet.c
+++ b/xen/arch/x86/hvm/hpet.c
@@ -404,7 +404,8 @@ static int cf_check hpet_write(
         break;
 
     case HPET_STATUS:
-        /* write 1 to clear. */
+        /* Write 1 to clear. Therefore don't use new_val directly here. */
+        new_val = val << ((addr & 7) * 8);
         while ( new_val )
         {
             bool active;
--
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