[Xen-devel] RE: Genapic testing

["Puthiyaparambil, Aravindh" <aravindh.puthiyaparambil@xxxxxxxxxx>]

> Are the TSCs on all CPUs suitably sync'ed up? If the PIT is firing and
> we are updating our timestamp info often enough, and all CPUs have
> similar TSC values, then all should work okay. Don Fry has a patch
that
> handles unsync'ed TSCs, if that turns out to be the problem.

On native Linux the skew is reported and is "fixed up". But that does
not mean the TSC was really adjusted, it will keep running with this
gap. So the CPU TSC skew could be the problem. The only difference is
that for Xen, the skew for the boot CPU is unusually high.

This is the output on native Linux:

checking TSC synchronization across 16 CPUs:
BIOS BUG: CPU#0 improperly initialized, has 360475 usecs TSC skew!
FIXED.
BIOS BUG: CPU#1 improperly initialized, has 360486 usecs TSC skew!
FIXED.
BIOS BUG: CPU#2 improperly initialized, has 360476 usecs TSC skew!
FIXED.
BIOS BUG: CPU#3 improperly initialized, has 360475 usecs TSC skew!
FIXED.
BIOS BUG: CPU#4 improperly initialized, has -360478 usecs TSC skew!
FIXED.
BIOS BUG: CPU#5 improperly initialized, has -360479 usecs TSC skew!
FIXED.
BIOS BUG: CPU#6 improperly initialized, has -360479 usecs TSC skew!
FIXED.
BIOS BUG: CPU#7 improperly initialized, has -360479 usecs TSC skew!
FIXED.
BIOS BUG: CPU#8 improperly initialized, has 360484 usecs TSC skew!
FIXED.
BIOS BUG: CPU#9 improperly initialized, has 360483 usecs TSC skew!
FIXED.
BIOS BUG: CPU#10 improperly initialized, has 360476 usecs TSC skew!
FIXED.
BIOS BUG: CPU#11 improperly initialized, has 360475 usecs TSC skew!
FIXED.
BIOS BUG: CPU#12 improperly initialized, has -360478 usecs TSC skew!
FIXED.
BIOS BUG: CPU#13 improperly initialized, has -360479 usecs TSC skew!
FIXED.
BIOS BUG: CPU#14 improperly initialized, has -360479 usecs TSC skew!
FIXED.
BIOS BUG: CPU#15 improperly initialized, has -360479 usecs TSC skew!
FIXED.

This is the output for Xen:

(XEN) checking TSC synchronization across 16 CPUs:
(XEN) CPU#0 had 47220790 usecs TSC skew, fixed it up.
(XEN) CPU#1 had 2298443 usecs TSC skew, fixed it up.
(XEN) CPU#2 had 2298445 usecs TSC skew, fixed it up.
(XEN) CPU#3 had 2298440 usecs TSC skew, fixed it up.
(XEN) CPU#4 had -2298445 usecs TSC skew, fixed it up.
(XEN) CPU#5 had -2298444 usecs TSC skew, fixed it up.
(XEN) CPU#6 had -2298445 usecs TSC skew, fixed it up.
(XEN) CPU#7 had -2298444 usecs TSC skew, fixed it up.
(XEN) CPU#8 had 2298454 usecs TSC skew, fixed it up.
(XEN) CPU#9 had 2298443 usecs TSC skew, fixed it up.
(XEN) CPU#10 had 2298450 usecs TSC skew, fixed it up.
(XEN) CPU#11 had 2298440 usecs TSC skew, fixed it up.
(XEN) CPU#12 had -2298445 usecs TSC skew, fixed it up.
(XEN) CPU#13 had -2298442 usecs TSC skew, fixed it up.
(XEN) CPU#14 had -2298445 usecs TSC skew, fixed it up.
(XEN) CPU#15 had -2298444 usecs TSC skew, fixed it up.

Maybe the patch that handles unsync'ed TSCs could solve this issue.

Aravindh

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