[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] RE: [Xen-devel] [patch] pae: tlbflush linear page table updates
>From: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx >[mailto:xen-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of Keir Fraser >Sent: Wednesday, August 10, 2005 9:12 PM >On 10 Aug 2005, at 14:01, Gerd Knorr wrote: > >>> Sure? The patch below fixes it for me. >> >> Uhm, well, it doesn't really fix it. >> >>> The tlbflush stuff is red herring btw, the real difference is >>> optimization. Build with "optimize=n" boot fine, others don't. >> >> While looking into this I've noticed the bug comes and goes away >> with the optimization level. Building with -O1 works fine, >> building with -O2 breaks (both with the patch mailed applied). >> >> There might be something wrong with the inline assembler ... > >See the fix I just this minute checked in :-) > >Hopefully it should fix all these weirdnesses.... > > -- Keir Is similar fix also required by __put_user_64? #define __put_user_u64(x, addr, retval, errret) \ ... : "=r"(retval) \ : "A" (x), "r" (addr), "i"(errret), "0"(retval)) I'm not sure exact rules for compiler to choose registers. But once compiler optimizes retval or addr to reuse eax/edx under some condition, user will also see either incorrect return value, or incorrect content written to incorrect address. Can we assume such optimization never happen? Thanks, Kevin _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
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