RE: [Xen-devel] RE: event delay issue on SMP machine when xen0 is SMPenabled

["Tian, Kevin" <kevin.tian@xxxxxxxxx>]

>From: Li, Xin B
>Sent: 2005年12月9日 16:50
>
>>> BTW, why vcpu other than vcpu0 won't handle event by default?
>>
>>We could allow any vcpu to process any pending notifications. It would
>>mean vcpus outside an irq's affinity set could end up processing an
>>interrupt and I'm not sure if that's a good thing. It would actually
>>slightly simplify evtchn.c though (no need to apply a per-cpu mask to
>>the event-channel port array).
>>
>
>I have a question on the following function, why l1 is updated only one
>time, while l2 is updated in each loop? I think they should handle in
>the same way. Anyway, in current code, l2 &= ~(1UL << l2i); is not
>needed.

Does that mean in the middle of processing l2, some bits previously active may 
become inactive due to unmasked by other vcpus? So conservative check in each 
loop may be necessary. ;-)

Thanks,
Kevin

>Thanks
>-Xin
>
>/* NB. Interrupts are disabled on entry. */
>asmlinkage void evtchn_do_upcall(struct pt_regs *regs)
>{
>       unsigned long  l1, l2;
>       unsigned int   l1i, l2i, port;
>       int            irq, cpu = smp_processor_id();
>       shared_info_t *s = HYPERVISOR_shared_info;
>       vcpu_info_t   *vcpu_info = &s->vcpu_info[cpu];
>
>       vcpu_info->evtchn_upcall_pending = 0;
>
>       /* NB. No need for a barrier here -- XCHG is a barrier on x86.
>*/
>       l1 = xchg(&vcpu_info->evtchn_pending_sel, 0);
>       while (l1 != 0) {
>               l1i = __ffs(l1);
>               l1 &= ~(1UL << l1i);
>
>               while ((l2 = active_evtchns(cpu, s, l1i)) != 0) {
>                       l2i = __ffs(l2);
>                       l2 &= ~(1UL << l2i);
>
>                       port = (l1i * BITS_PER_LONG) + l2i;
>                       if ((irq = evtchn_to_irq[port]) != -1)
>                               do_IRQ(irq, regs);
>                       else
>                               evtchn_device_upcall(port);
>               }
>       }
>}
>
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