Re: [Xen-devel] [PATCH] i386 linux: make 32-bit PAE kernel work when built with newer gcc

[Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>]

> > 1. Compiler causes high to be cleared before low.
> > 2. This causes an invalid PTE (e.g., pointing into an uncacheable I/O
> > region)
> > 3. A processor speculatively loads the PTE into its TLB
> > 4. A processor speculatively fetches a cacheline from the bogus area
> > 5. You get a bug like the old AMD GART hang, where the CPU writes back
> > the cache line at an inopportune moment, when it should never have 
> > been
> > cached in the first place.
> It, at least as per the spec, cannot write this cache line back, as 
> everything
> up to here was speculative, and hence no change to the cache line may 
> have
> occurred. But the caching inconsistencies would still be a problem and 
> could,
> if I recall right, lead to processor hangs.
> If such a speculative access is considered theoretically possible, 
> then yes, I'd
> think the same change is needed for native.
Not sure which spec you refer to but it definitely can happen, as 
demonstrated by the infamous AMD GART problem some time back:
http://lwn.net/2002/0124/a/athlon-agp-problem.php3

The above link gives plenty of detail, but briefly: The processor can 
speculatively decide it's found a store instruction and thus 
write-allocate an arbitrary cache line. This line will ultimately get 
written back even if the speculative store never actually gets 
executed.
 -- Keir


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