RE: [Xen-devel] how can native driver response quickly for low FIFO device

["Dong, Eddie" <eddie.dong@xxxxxxxxx>]

> 
> There's a 128-byte receive buffer. Bytes are greedily taken from the
> UART FIFO in interrupt context and written to the software receive
> buffer. If overflow were a problem we could obviously quite easily
> make that receive buffer substantially larger.
But this need the participate of processor in dom0. If the physical
processor is running for domU, and domU is waiting for its time slice
(descheduled), how can the bytes be taken to software receive buffer?
Eddie

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