[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

RE: [Xen-devel] [PATCH] [HVM] Fix virtual apic irq distribution

  • To: "Keir Fraser" <Keir.Fraser@xxxxxxxxxxxx>
  • From: "Li, Xin B" <xin.b.li@xxxxxxxxx>
  • Date: Tue, 27 Jun 2006 19:39:00 +0800
  • Cc: xen-devel@xxxxxxxxxxxxxxxxxxx
  • Delivery-date: Tue, 27 Jun 2006 05:04:46 -0700
  • List-id: Xen developer discussion <xen-devel.lists.xensource.com>
  • Thread-index: AcaZz4mIM3FINp5ARu+XolTx6C1t5AACyaMQ
  • Thread-topic: [Xen-devel] [PATCH] [HVM] Fix virtual apic irq distribution

>> Fix virtual apic irq distribution.
>> But currently we inject PIT irqs to cpu0 only. Also mute some warning
>> messages.
>Does anything break if we inject PIT irqs to other than cpu0? It seems 
>an odd restriction -- native hardware wouldn't treat that line 
>specially if IRQ0 is routed through the IO-APIC, would it?

You're right, on native hardware, PIT irq can be routed to any
processor, and usually PIT irq handler will keep OS time by checking
TSC.  On native hardware, TSC are naturally synchronized across
processors, so it won't be trouble.
But on our VM, we will have to synchronize TSC from time to time, so PIT
irq handler on different vcpu may see big TSC diff and complain about
the unreliable TSC, then maybe it will try to do TSC sync, which make
guest time keeping complex and unreliable.
Ideally, we should not have this restriction, but for now I think this
can make guest time keeping simple and reliable, and I think Eddie
should have more comments on this :-)

Xen-devel mailing list



Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.