[Xen-devel] [PATCH] Make AMD GART work as a mini IOMMU [1/4]

["Langsdorf, Mark" <mark.langsdorf@xxxxxxx>]

Every AMD processor has an AGP aperture and 
Graphics Address Transalation Table (GART) built
into its Northbridge.  The aperture is a
physically contiguous range of memory addresses
under 0xFFFFFFFF that devices can write to; the
GART is a table that translates GART addresses 
into defined virtual addresses.  A DMA device 
can transfer data through the aperture using
32-bit accesses and have the processor automatically
transfer the data to system memory above 4GB without
needing to use software bounce buffering.  On
systems using 32-bit DMA devices, it can speed 
up I/O performance by 15-20% or more.

This patch set enables the AGP aperture and GART
in Xen dom0.  In order to do that easily and 
without interfering with the swiotlb code, it
enables dma_ops for dom0 guests and modifies 
the x86_64 pci-swiotlb-xen.c code to work with
dma_ops.

The first patch creates the 
arch/x86_64/kernel/pci-dma-xen.c file based on the 
standard pci-dma.c.

The second patch modifies 
arch/x86_64/kernel/pci-swiotlb-xen.c to work with 
dma_ops, and modifies arch/x86_64/kernel/pci-dma-xen.c
slightly to be Xen-safe by copying over some functions
from arch/i386/kernel/pci-dma-xen.c.

The third patch creates the 
arch/x86_64/kernel/pci-gart-xen.c and
arch/x86_64/kernel/aperture-xen.c files based on the
standard pci-gart.c and aperture.c files.

The fourth patch modifies pci-gart-xen.c and 
aperture-xen.c to work with Xen.  It adds a
hypervisor call to clear the aperture address
range from the hypervisor's memory tables,
which is necessary to avoid a cache coherency
issue, and ups the range of contiguous memory
that Xen provides, which is necessary since
the aperture must be at least 32 MB.

Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxx>

-Mark Langsdorf
AMD, Inc.
-Mark Langsdorf
AMD, Inc.

Attachment: add-x86_64-pci-dma-xen.patch
Description: add-x86_64-pci-dma-xen.patch

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