[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] Question regarding the number of P2M l3e entries
In p2m.c (line 197
and line 550), the code assumes the number of L3 P2M table entries is 8 (under
PAE mode). According to Intel and AMD specs, it is 4. Could someone explain
this discrepancy? Is it a bug?
-Wei
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