[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] vmx & efer
On 7/5/07 09:57, "Jan Beulich" <jbeulich@xxxxxxxxxx> wrote: >> You seem to be assuming that if the hypervisor executes with 4-level >> pagetables then so must all VMX guests. This isn't true. A VMX VCPU running >> in 32-bit mode (PAE or not) will execute with 3-level pagetables when >> running on x86/64 Xen. > > Oh, okay, I didn't realize that. That makes things look consistent again, as > long > as you are saying that in this mode the physical CR3 continues to be a 64-bit > register? That I'm not sure about. We always ensure the shadow PAE CR3 is in low 4GB, so we don't have to worry about this. I guess it depends whether PAE CR3 is 32-bit because of microarchitectural assumptions, or merely because in 32-bit mode there is no way to write more than 32 bits to a control register. -- Keir _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
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