RE: [Xen-devel] [PATCH] [HVM][SVM] Handle threshold register for guests

["Petersson, Mats" <Mats.Petersson@xxxxxxx>]

> -----Original Message-----
> From: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx 
> [mailto:xen-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of 
> Keir Fraser
> Sent: 24 May 2007 11:46
> To: Egger, Christoph; xen-devel@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [Xen-devel] [PATCH] [HVM][SVM] Handle threshold 
> register for guests
> 
> On 21/5/07 18:24, "Christoph Egger" <Christoph.Egger@xxxxxxx> wrote:
> 
> > The threshold register has been introduced in AMD RevF CPUs 
> along with SVM
> > (Actually this MCA/MCE msr register existed before, but had 
> no meaning).
> > Therefore no need for additional cpuid checks.
> > 
> > On read access it reports the HVM guest the register has 
> been locked by the
> > BIOS. This means, it is not available for OS use. Thus, 
> write accesses are
> > simply ignored.
> > This behaviour actually matches real HW, so guests can deal 
> with this.
> > 
> > Further, this way no multiplexing for multiple guests is necessary.
> > Please apply.
> 
> I can't find any information about the revised semantics of 
> M4_MISC in the
> latest revision (3.12) of Volume 2 of the AMD64 Architecture 
> Programmer's
> Manual. Am I looking in the wrong place?
> 
> Since we don't advertise SVM capability to guests, wouldn't 
> they assume old
> semantics for this register anyway?

Yes, you're looking in the wrong place the APM is for "generic
functionality", the BIOS and Kernel Developer's Guide (BKDG) is more
specific as to implementation details for the different generations, and
on page 225 [public version], you'll find the details of this register. 

http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/
32559.pdf

As to whether the processor expects this behaviour or not is a different
question. But let's say they use the family/model CPUID info to identify
if this feature is available or not, rather than the more loosely
coupled feature-bit of SVM (e.g. a Sempron Rev F processor would have
the functionality in this register, but no SVM bit set as it's not got
SVM-feature). 

I think the patch is OK to support any future OS that MAY try to use
this register. It's not harming anything, right?

--
Mats
> 
>  Thanks,
>  Keir
> 
> 
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> 



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