RE: [Xen-devel] Hypercalls in Intel-VT

["Dong, Eddie" <eddie.dong@xxxxxxxxx>]

GDTR BASE & Limit are part of Host/Guest state which will be save/restored.

Eddie

---

From: Ashish Bijlani [mailto:ashish.bijlani@xxxxxxxxx]
Sent: 2007年10月29日 6:19
To: Tim Deegan
Cc: Mark Williamson; xen-devel@xxxxxxxxxxxxxxxxxxx; Dong, Eddie
Subject: Re: [Xen-devel] Hypercalls in Intel-VT

does transition from non-root VMX mode to root VMX mode require GDT 
switch i.e. does GDT change from guest OS krnl's GDT to xen's GDT?

On 10/28/07, Tim Deegan <Tim.Deegan@xxxxxxxxxxxxx> wrote:

At 02:55 +0100 on 27 Oct (1193453721), Mark Williamson wrote:
> Regarding the TLB flush, again, the hardware quite possibly does that.  But
> I'm not aware of anything in the VMX spec that exposes this detail, so Intel
> could easily tag the TLB entries as root / non-root to avoid flushing on a
> VMEXIT / VMENTER.  For all I know, they may do this already!

Right now, Intel processors always flush the whole TLB (including global
entries) on a transition to or from non-root mode.  Newer AMD processors
have tagged TLBs so you can do an exit/enter without flushing, but you
have to explicitly discard the guest entries when it's appropriate.  (Look
at arch/x86/hvm/svm/asid.c).  That's on the road map for Intel too, I
believe.

Cheers,

Tim.

--
Tim Deegan <Tim.Deegan@xxxxxxxxxxxxx>, XenSource UK Limited
Registered office c/o EC2Y 5EB, UK; company number 05334508

_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-devel