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[Xen-devel] Re: Question on virtual HPET's behavior

  • To: "Shan, Haitao" <haitao.shan@xxxxxxxxx>
  • From: Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>
  • Date: Wed, 26 Dec 2007 14:48:37 +0000
  • Cc: xen-devel@xxxxxxxxxxxxxxxxxxx
  • Delivery-date: Wed, 26 Dec 2007 06:42:28 -0800
  • List-id: Xen developer discussion <xen-devel.lists.xensource.com>
  • Thread-index: AchHvBbtVyfWSh9jR1ygGG/txsMeigACoOB5AABrrCAAAYcR6w==
  • Thread-topic: Question on virtual HPET's behavior

The only reason I can think of why Linux writes twice, and indeed has a udelay(1) between the two writes these days, is because some hardware implementations only allow access to one of comparator and period on each write, and never both. But the ICH9 behaviour doesn’t appear to violate the spec either (in fact possibly the spec seems more in line with ICH9 behaviour).

Perhaps you can ask the right team within Intel what the intended semantics is, or whether it is defined at all?

 -- Keir

On 26/12/07 14:19, "Shan, Haitao" <haitao.shan@xxxxxxxxx> wrote:

No. I did not see such an OS. My concern is: When VAL_SET_CNF is set, do the two registers all get updated? The spec does provide information. From our tests, if you strictly follow the sequence attached in my first mail, the comparator can keep increasing normally. With virtual HPET, it is not true, because period is not considered to be set by only one write. Our tests are carried out on ICH9.
This leads me to confusion. Which one is the right behavior? Writing twice should guarantee the correctness, but is it a must?

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