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RE: [Xen-devel] Problems with enabling hypervisor C and P-state control

  • To: 'Niraj Tolia' <ntolia@xxxxxxxxx>, "Yu, Ke" <ke.yu@xxxxxxxxx>
  • From: "Tian, Kevin" <kevin.tian@xxxxxxxxx>
  • Date: Tue, 28 Oct 2008 09:04:25 +0800
  • Accept-language: en-US
  • Acceptlanguage: en-US
  • Cc: "Liu, Jinsong" <jinsong.liu@xxxxxxxxx>, Xen Developers <xen-devel@xxxxxxxxxxxxxxxxxxx>
  • Delivery-date: Mon, 27 Oct 2008 18:05:30 -0700
  • List-id: Xen developer discussion <xen-devel.lists.xensource.com>
  • Thread-index: Ack4XfzZR5Mdq1xOQc21du2XH2OXjgAOphqw
  • Thread-topic: [Xen-devel] Problems with enabling hypervisor C and P-state control

>From: Niraj Tolia [mailto:ntolia@xxxxxxxxx] 
>Sent: Tuesday, October 28, 2008 2:01 AM
>On Thu, Oct 23, 2008 at 10:59 PM, Yu, Ke <ke.yu@xxxxxxxxx> wrote:
>> After discussing with Jinsong, we got the root cause. You 
>are right, this is xen pm statistics logic issue. when the 
>coordination type is SW_ANY, we only record the first CPU 
>cpufreq change, the other 3 cores within the same dependency 
>domain is ignored, so you only see one core changes every 
>dependency domain.
>> The attached patch fix  this issue. could you please have a 
>try? If it works in your platform, we will send out for 
>applying in upstream.
>I just applied the patch and while xenpm might be doing the right
>thing, I am not completely sure. For example, if I launch a single
>VCPU VM, pin it to a core, and launch a CPU intensive task on it, ALL
>four cores on the socket are reported to switch into P0. However, from
>what I understand about this processor (Xeon E7330), only two of them
>should. Like vanilla Linux, the other two should be able to operate at
>independent voltage/frequency settings. Once again, I am not sure if
>this is xenpm's fault or if the underlying frequency control code
>isn't able to determine what  CPUs need to switch frequency at the
>same time.

Do you change any BIOS setting when comparing native Linux and
Xen? From the xen dmesg you posted last time:
(XEN)   _PSD: num_entries=5 rev=0 domain=1 coord_type=253 num_processors=4
(XEN)   _PSD: num_entries=5 rev=0 domain=2 coord_type=253 num_processors=4
(XEN)   _PSD: num_entries=5 rev=0 domain=3 coord_type=253 num_processors=4
You can see that BIOS reports 4 processors in a dependent domain
with a SW_ANY coordination type. It means that any cpu within
given dependent domain changes freq, all the rest 3 cpus change too.


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