[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 0/6] MSI-INTx interrupt translation for HVM
On Thu, 8 Jan 2009 22:52:00 +0800 Qing He <qing.he@xxxxxxxxx> wrote: > On Thu, 2009-01-08 at 18:44 +0800, Shohei Fujiwara wrote: > > I have one question. > > > > MSI interrupt is edge-triggered, and INTx interrupt is level-triggered. > > Guest OS handles translated interrupt as level-triggered, though physical > > interrupt is edge-triggered. When two interrupts are raised during short > > period, Guest OS might lose 2nd interrupt, I think. > > This problem is handled by a different EOI timing. As soon as the > hypervisor receives an MSI, it issues the EOI ASAP, and the duration of > the injected level-triggered IRQ and guest EOI are all handled by the > virtual APICs. If a 2nd interrupt comes up at this time, the hypervisor > can receive the EOI and this results in a pending IRQ in virtual APICs > instead of lost. I found hypervisor doesn't issue EOI before injecting the interrupt to guest domain, if MSI isn't maskable. The 2nd interrupt may be lost. What do you think about this? xen/arch/x86/irq.c: asmlinkage void do_IRQ(struct cpu_user_regs *regs) { unsigned int vector = regs->entry_vector; irq_desc_t *desc = &irq_desc[vector]; struct irqaction *action; perfc_incr(irqs); spin_lock(&desc->lock); desc->handler->ack(vector); xen/arch/x86/io_apic.c: static void ack_msi_vector(unsigned int vector) { if ( msi_maskable_irq(irq_desc[vector].msi_desc) ) ack_APIC_irq(); /* ACKTYPE_NONE */ } Thanks, -- Shohei Fujiwara _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
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