[Xen-devel] [PATCH][ioemu] support the assignment of the VF of Intel 82599 10GbE Controller

["Cui, Dexuan" <dexuan.cui@xxxxxxxxx>]

The datasheet is available at
http://download.intel.com/design/network/datashts/82599_datasheet.pdf

See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the PCI
Express Capability Structure of the VF of Intel 82599 10GbE Controller looks
trivial, e.g., the PCI Express Capabilities Register is 0, so the Capability
Version is 0 and pt_pcie_size_init() would fail.

We should not try to expose the PCIe cap of the device to guest.

Signed-off-by: Dexuan Cui <dexuan.cui@xxxxxxxxx>

diff --git a/hw/pass-through.c b/hw/pass-through.c
index f3d033b..360f2a1 100644
--- a/hw/pass-through.c
+++ b/hw/pass-through.c
@@ -2408,6 +2408,25 @@ out:
     return err;
 }
 
+/* A return value of 1 means the capability should NOT be exposed to guest. */
+static int pt_hide_dev_cap(const struct pci_dev *dev, uint8_t grp_id)
+{
+    switch (grp_id)
+    {
+    case PCI_CAP_ID_EXP:
+        /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
+         * Controller looks trivial, e.g., the PCI Express Capabilities
+         * Register is 0. We should not try to expose it to guest.
+         */
+        if (dev->vendor_id == PCI_VENDOR_ID_INTEL &&
+                dev->device_id == PCI_DEVICE_ID_INTEL_82599_VF)
+            return 1;
+        break;
+    }
+
+    return 0;
+}
+
 /* initialize emulate register group */
 static int pt_config_init(struct pt_dev *ptdev)
 {
@@ -2424,6 +2443,9 @@ static int pt_config_init(struct pt_dev *ptdev)
     {
         if (pt_emu_reg_grp_tbl[i].grp_id != 0xFF)
         {
+            if (pt_hide_dev_cap(ptdev->pci_dev, pt_emu_reg_grp_tbl[i].grp_id))
+                continue;
+
             reg_grp_offset = (uint32_t)find_cap_offset(ptdev->pci_dev,
                                  pt_emu_reg_grp_tbl[i].grp_id);
             if (!reg_grp_offset)
@@ -2556,6 +2578,8 @@ static uint32_t pt_ptr_reg_init(struct pt_dev *ptdev,
             /* check whether the next capability
              * should be exported to guest or not
              */
+            if (pt_hide_dev_cap(ptdev->pci_dev, pt_emu_reg_grp_tbl[i].grp_id))
+                continue;
             if (pt_emu_reg_grp_tbl[i].grp_id == ptdev->dev.config[reg_field])
             {
                 if (pt_emu_reg_grp_tbl[i].grp_type == GRP_TYPE_EMU)
diff --git a/hw/pci.h b/hw/pci.h
index 30bcb04..de5a4e1 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -112,6 +112,7 @@ extern target_phys_addr_t pci_mem_base;
 #define PCI_DEVICE_ID_INTEL_82371AB      0x7111
 #define PCI_DEVICE_ID_INTEL_82371AB_2    0x7112
 #define PCI_DEVICE_ID_INTEL_82371AB_3    0x7113
+#define PCI_DEVICE_ID_INTEL_82599_VF     0x10ed
 
 #define PCI_VENDOR_ID_FSL                0x1957
 #define PCI_DEVICE_ID_FSL_E500           0x0030

Attachment: hide_pcie_cap_of_intel_82599.patch.txt
Description: hide_pcie_cap_of_intel_82599.patch.txt

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