[Xen-devel] Re: [Qemu-devel] [PATCH 15/15] xen: Add a Xen specific ACPI Implementation to target-xen

[Blue Swirl <blauwirbel@xxxxxxxxx>]

On Thu, Aug 12, 2010 at 2:10 PM,  <stefano.stabellini@xxxxxxxxxxxxx> wrote:
> From: Anthony PERARD <anthony.perard@xxxxxxxxxx>
>
> Xen currently uses a different BIOS (hvmloader + rombios) therefore the
> Qemu acpi_piix4 implementation wouldn't work correctly with Xen.
> We plan on fixing this properly but at the moment we are just adding a
> new Xen specific acpi_piix4 implementation.

I'd suppose the proper fix is to modify acpi_piix4 instead of copy&paste.

> This patch is optional; without it the VM boots but it cannot shutdown
> properly or go to S3.
>
> Signed-off-by: Anthony PERARD <anthony.perard@xxxxxxxxxx>
> Signed-off-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
> ---
> ÂMakefile.target   |  Â1 +
> Âhw/xen_acpi_piix4.c | Â424 
> +++++++++++++++++++++++++++++++++++++++++++++++++++
> Âhw/xen_common.h   |  Â3 +
> Âhw/xen_machine_fv.c | Â Â6 +-
> Â4 files changed, 429 insertions(+), 5 deletions(-)
> Âcreate mode 100644 hw/xen_acpi_piix4.c
>
> diff --git a/Makefile.target b/Makefile.target
> index 1984cdd..a2d9217 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -325,6 +325,7 @@ obj-xen-y += piix_pci.o
> Âobj-xen-y += mc146818rtc.o
> Âobj-xen-y += xenstore.o
> Âobj-xen-y += xen_platform.o
> +obj-xen-y += xen_acpi_piix4.o
>
> Âobj-xen-y += xen_mapcache.o
> Âobj-xen-y += stub-functions.o
> diff --git a/hw/xen_acpi_piix4.c b/hw/xen_acpi_piix4.c
> new file mode 100644
> index 0000000..3c65963
> --- /dev/null
> +++ b/hw/xen_acpi_piix4.c
> @@ -0,0 +1,424 @@
> + /*
> + * PIIX4 ACPI controller emulation
> + *
> + * Winston liwen Wang, winston.l.wang@xxxxxxxxx
> + * Copyright (c) 2006 , Intel Corporation.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> + * of this software and associated documentation files (the "Software"), to 
> deal
> + * in the Software without restriction, including without limitation the 
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw.h"
> +#include "pc.h"
> +#include "pci.h"
> +#include "sysemu.h"
> +#include "acpi.h"
> +
> +#include "xen_backend.h"
> +#include "xen_common.h"
> +#include "qemu-log.h"
> +
> +#include <xen/hvm/ioreq.h>
> +#include <xen/hvm/params.h>
> +
> +#define PIIX4ACPI_LOG_ERROR 0
> +#define PIIX4ACPI_LOG_INFO 1
> +#define PIIX4ACPI_LOG_DEBUG 2
> +#define PIIX4ACPI_LOGLEVEL PIIX4ACPI_LOG_INFO
> +#define PIIX4ACPI_LOG(level, fmt, ...) do { if (level <= PIIX4ACPI_LOGLEVEL) 
> qemu_log(fmt, ## __VA_ARGS__); } while (0)
> +
> +/* Sleep state type codes as defined by the \_Sx objects in the DSDT. */
> +/* These must be kept in sync with the DSDT (hvmloader/acpi/dsdt.asl) */
> +#define SLP_TYP_S4 Â Â Â Â(6 << 10)
> +#define SLP_TYP_S3 Â Â Â Â(5 << 10)
> +#define SLP_TYP_S5 Â Â Â Â(7 << 10)
> +
> +#define ACPI_DBG_IO_ADDR Â0xb044
> +#define ACPI_PHP_IO_ADDR Â0x10c0
> +
> +#define PHP_EVT_ADD Â Â 0x0
> +#define PHP_EVT_REMOVE Â0x3
> +
> +/* The bit in GPE0_STS/EN to notify the pci hotplug event */
> +#define ACPI_PHP_GPE_BIT 3
> +
> +#define DEVFN_TO_PHP_SLOT_REG(devfn) (devfn >> 1)
> +#define PHP_SLOT_REG_TO_DEVFN(reg, hilo) ((reg << 1) | hilo)
> +
> +/* ioport to monitor cpu add/remove status */
> +#define PROC_BASE 0xaf00
> +
> +typedef struct PCIAcpiState {
> + Â ÂPCIDevice dev;
> + Â Âuint16_t pm1_control; /* pm1a_ECNT_BLK */
> + Â Âqemu_irq irq;
> + Â Âqemu_irq cmos_s3;
> +} PCIAcpiState;
> +
> +typedef struct GPEState {
> + Â Â/* GPE0 block */
> + Â Âuint8_t gpe0_sts[ACPI_GPE0_BLK_LEN / 2];
> + Â Âuint8_t gpe0_en[ACPI_GPE0_BLK_LEN / 2];
> +
> + Â Â/* CPU bitmap */
> + Â Âuint8_t cpus_sts[32];
> +
> + Â Â/* SCI IRQ level */
> + Â Âuint8_t sci_asserted;
> +
> +} GPEState;
> +
> +static GPEState gpe_state;
> +
> +static qemu_irq sci_irq;
> +
> +typedef struct AcpiDeviceState AcpiDeviceState;
> +AcpiDeviceState *acpi_device_table;
> +
> +static const VMStateDescription vmstate_acpi = {
> + Â Â.name = "PIIX4 ACPI",
> + Â Â.version_id = 1,
> +  Â.fields   Â= (VMStateField []) {
> + Â Â Â ÂVMSTATE_PCI_DEVICE(dev, PCIAcpiState),
> + Â Â Â ÂVMSTATE_UINT16(pm1_control, PCIAcpiState),
> + Â Â Â ÂVMSTATE_END_OF_LIST()
> + Â Â}
> +};
> +
> +static void acpiPm1Control_writeb(void *opaque, uint32_t addr, uint32_t val)
> +{
> + Â ÂPCIAcpiState *s = opaque;
> + Â Âs->pm1_control = (s->pm1_control & 0xff00) | (val & 0xff);
> +}
> +
> +static uint32_t acpiPm1Control_readb(void *opaque, uint32_t addr)
> +{
> + Â ÂPCIAcpiState *s = opaque;
> + Â Â/* Mask out the write-only bits */
> + Â Âreturn (uint8_t)(s->pm1_control & 
> ~(ACPI_BITMASK_GLOBAL_LOCK_RELEASE|ACPI_BITMASK_SLEEP_ENABLE));
> +}
> +
> +static void acpi_shutdown(PCIAcpiState *s, uint32_t val)
> +{
> + Â Âif (!(val & ACPI_BITMASK_SLEEP_ENABLE))
> + Â Â Â Âreturn;
> +
> + Â Âswitch (val & ACPI_BITMASK_SLEEP_TYPE) {
> + Â Âcase SLP_TYP_S3:
> + Â Â Â Âqemu_system_reset();
> + Â Â Â Âqemu_irq_raise(s->cmos_s3);
> + Â Â Â Âxc_set_hvm_param(xen_xc, xen_domid, HVM_PARAM_ACPI_S_STATE, 3);
> + Â Â Â Âbreak;
> + Â Âcase SLP_TYP_S4:
> + Â Âcase SLP_TYP_S5:
> + Â Â Â Âqemu_system_shutdown_request();
> + Â Â Â Âbreak;
> + Â Âdefault:
> + Â Â Â Âbreak;
> + Â Â}
> +}
> +
> +static void acpiPm1ControlP1_writeb(void *opaque, uint32_t addr, uint32_t 
> val)
> +{
> + Â ÂPCIAcpiState *s = opaque;
> +
> + Â Âval <<= 8;
> + Â Âs->pm1_control = ((s->pm1_control & 0xff) | val) & 
> ~ACPI_BITMASK_SLEEP_ENABLE;
> +
> + Â Âacpi_shutdown(s, val);
> +}
> +
> +static uint32_t acpiPm1ControlP1_readb(void *opaque, uint32_t addr)
> +{
> + Â ÂPCIAcpiState *s = opaque;
> + Â Â/* Mask out the write-only bits */
> + Â Âreturn (uint8_t)((s->pm1_control & 
> ~(ACPI_BITMASK_GLOBAL_LOCK_RELEASE|ACPI_BITMASK_SLEEP_ENABLE)) >> 8);
> +}
> +
> +static void acpiPm1Control_writew(void *opaque, uint32_t addr, uint32_t val)
> +{
> + Â ÂPCIAcpiState *s = opaque;
> +
> + Â Âs->pm1_control = val & ~ACPI_BITMASK_SLEEP_ENABLE;
> +
> + Â Âacpi_shutdown(s, val);
> +}
> +
> +static uint32_t acpiPm1Control_readw(void *opaque, uint32_t addr)
> +{
> + Â ÂPCIAcpiState *s = opaque;
> + Â Â/* Mask out the write-only bits */
> + Â Âreturn (s->pm1_control & 
> ~(ACPI_BITMASK_GLOBAL_LOCK_RELEASE|ACPI_BITMASK_SLEEP_ENABLE));
> +}
> +
> +static void acpi_map(PCIDevice *pci_dev, int region_num,
> + Â Â Â Â Â Â Â Â Â Â uint32_t addr, uint32_t size, int type)
> +{
> + Â ÂPCIAcpiState *d = (PCIAcpiState *)pci_dev;
> +
> + Â Â/* Byte access */
> + Â Âregister_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d);
> + Â Âregister_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d);
> + Â Âregister_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d);
> + Â Âregister_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d);
> +
> + Â Â/* Word access */
> + Â Âregister_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d);
> + Â Âregister_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d);
> +}
> +
> +static inline int test_bit(uint8_t *map, int bit)
> +{
> + Â Âreturn ( map[bit / 8] & (1 << (bit % 8)) );
> +}
> +
> +static inline void set_bit(uint8_t *map, int bit)
> +{
> + Â Âmap[bit / 8] |= (1 << (bit % 8));
> +}
> +
> +static inline void clear_bit(uint8_t *map, int bit)
> +{
> + Â Âmap[bit / 8] &= ~(1 << (bit % 8));
> +}
> +
> +static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
> +{
> + Â ÂPIIX4ACPI_LOG(PIIX4ACPI_LOG_DEBUG, "ACPI: DBG: 0x%08x\n", val);
> + Â ÂPIIX4ACPI_LOG(PIIX4ACPI_LOG_INFO, "ACPI:debug: write addr=0x%x, 
> val=0x%x.\n", addr, val);
> +}
> +
> +/* GPEx_STS occupy 1st half of the block, while GPEx_EN 2nd half */
> +static uint32_t gpe_sts_read(void *opaque, uint32_t addr)
> +{
> + Â ÂGPEState *s = opaque;
> +
> + Â Âreturn s->gpe0_sts[addr - ACPI_GPE0_BLK_ADDRESS];
> +}
> +
> +/* write 1 to clear specific GPE bits */
> +static void gpe_sts_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + Â ÂGPEState *s = opaque;
> + Â Âint hotplugged = 0;
> +
> + Â ÂPIIX4ACPI_LOG(PIIX4ACPI_LOG_DEBUG, "gpe_sts_write: addr=0x%x, 
> val=0x%x.\n", addr, val);
> +
> + Â Âhotplugged = test_bit(&s->gpe0_sts[0], ACPI_PHP_GPE_BIT);
> + Â Âs->gpe0_sts[addr - ACPI_GPE0_BLK_ADDRESS] &= ~val;
> + Â Âif ( s->sci_asserted &&
> + Â Â Â Â hotplugged &&
> + Â Â Â Â !test_bit(&s->gpe0_sts[0], ACPI_PHP_GPE_BIT)) {
> + Â Â Â ÂPIIX4ACPI_LOG(PIIX4ACPI_LOG_INFO, "Clear the GPE0_STS bit for ACPI 
> hotplug & deassert the IRQ.\n");
> + Â Â Â Âqemu_irq_lower(sci_irq);
> + Â Â}
> +
> +}
> +
> +static uint32_t gpe_en_read(void *opaque, uint32_t addr)
> +{
> + Â ÂGPEState *s = opaque;
> +
> + Â Âreturn s->gpe0_en[addr - (ACPI_GPE0_BLK_ADDRESS + ACPI_GPE0_BLK_LEN / 
> 2)];
> +}
> +
> +/* write 0 to clear en bit */
> +static void gpe_en_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + Â ÂGPEState *s = opaque;
> + Â Âint reg_count;
> +
> + Â ÂPIIX4ACPI_LOG(PIIX4ACPI_LOG_DEBUG, "gpe_en_write: addr=0x%x, 
> val=0x%x.\n", addr, val);
> + Â Âreg_count = addr - (ACPI_GPE0_BLK_ADDRESS + ACPI_GPE0_BLK_LEN / 2);
> + Â Âs->gpe0_en[reg_count] = val;
> + Â Â/* If disable GPE bit right after generating SCI on it,
> + Â Â * need deassert the intr to avoid redundant intrs
> + Â Â */
> + Â Âif ( s->sci_asserted &&
> + Â Â Â Â reg_count == (ACPI_PHP_GPE_BIT / 8) &&
> + Â Â Â Â !(val & (1 << (ACPI_PHP_GPE_BIT % 8))) ) {
> + Â Â Â ÂPIIX4ACPI_LOG(PIIX4ACPI_LOG_INFO, "deassert due to disable GPE 
> bit.\n");
> + Â Â Â Âs->sci_asserted = 0;
> + Â Â Â Âqemu_irq_lower(sci_irq);
> + Â Â}
> +
> +}
> +
> +static void gpe_save(QEMUFile* f, void* opaque)
> +{
> + Â ÂGPEState *s = (GPEState*)opaque;
> + Â Âint i;
> +
> + Â Âfor ( i = 0; i < ACPI_GPE0_BLK_LEN / 2; i++ ) {
> + Â Â Â Âqemu_put_8s(f, &s->gpe0_sts[i]);
> + Â Â Â Âqemu_put_8s(f, &s->gpe0_en[i]);
> + Â Â}
> +
> + Â Âqemu_put_8s(f, &s->sci_asserted);
> + Â Âif ( s->sci_asserted ) {
> + Â Â Â ÂPIIX4ACPI_LOG(PIIX4ACPI_LOG_INFO, "gpe_save with sci asserted!\n");
> + Â Â}
> +}
> +
> +static int gpe_load(QEMUFile* f, void* opaque, int version_id)
> +{
> + Â ÂGPEState *s = (GPEState*)opaque;
> + Â Âint i;
> + Â Âif (version_id != 1)
> + Â Â Â Âreturn -EINVAL;
> +
> + Â Âfor ( i = 0; i < ACPI_GPE0_BLK_LEN / 2; i++ ) {
> + Â Â Â Âqemu_get_8s(f, &s->gpe0_sts[i]);
> + Â Â Â Âqemu_get_8s(f, &s->gpe0_en[i]);
> + Â Â}
> +
> + Â Âqemu_get_8s(f, &s->sci_asserted);
> + Â Âreturn 0;
> +}
> +
> +static uint32_t gpe_cpus_readb(void *opaque, uint32_t addr)
> +{
> + Â Âuint32_t val = 0;
> + Â ÂGPEState *g = opaque;
> +
> + Â Âswitch (addr) {
> + Â Â Â Âcase PROC_BASE ... PROC_BASE+31:
> + Â Â Â Â Â Âval = g->cpus_sts[addr - PROC_BASE];
> + Â Â Â Âdefault:
> + Â Â Â Â Â Âbreak;
> + Â Â}
> +
> + Â Âreturn val;
> +}
> +
> +static void gpe_cpus_writeb(void *opaque, uint32_t addr, uint32_t val)
> +{
> + Â Â/* GPEState *g = opaque; */
> +
> + Â Âswitch (addr) {
> + Â Â Â Âcase PROC_BASE ... PROC_BASE + 31:
> + Â Â Â Â Â Â/* don't allow to change cpus_sts from inside a guest */
> + Â Â Â Â Â Âbreak;
> + Â Â Â Âdefault:
> + Â Â Â Â Â Âbreak;
> + Â Â}
> +}
> +
> +static void gpe_acpi_init(void)
> +{
> + Â ÂGPEState *s = &gpe_state;
> + Â Âmemset(s, 0, sizeof(GPEState));
> +
> + Â Âs->cpus_sts[0] = 1;
> +
> + Â Âregister_ioport_read(PROC_BASE, 32, 1, Âgpe_cpus_readb, s);
> + Â Âregister_ioport_write(PROC_BASE, 32, 1, gpe_cpus_writeb, s);
> +
> + Â Âregister_ioport_read(ACPI_GPE0_BLK_ADDRESS,
> + Â Â Â Â Â Â Â Â Â Â Â Â ACPI_GPE0_BLK_LEN / 2,
> + Â Â Â Â Â Â Â Â Â Â Â Â 1,
> + Â Â Â Â Â Â Â Â Â Â Â Â gpe_sts_read,
> + Â Â Â Â Â Â Â Â Â Â Â Â s);
> + Â Âregister_ioport_read(ACPI_GPE0_BLK_ADDRESS + ACPI_GPE0_BLK_LEN / 2,
> + Â Â Â Â Â Â Â Â Â Â Â Â ACPI_GPE0_BLK_LEN / 2,
> + Â Â Â Â Â Â Â Â Â Â Â Â 1,
> + Â Â Â Â Â Â Â Â Â Â Â Â gpe_en_read,
> + Â Â Â Â Â Â Â Â Â Â Â Â s);
> +
> + Â Âregister_ioport_write(ACPI_GPE0_BLK_ADDRESS,
> + Â Â Â Â Â Â Â Â Â Â Â Â ÂACPI_GPE0_BLK_LEN / 2,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â1,
> + Â Â Â Â Â Â Â Â Â Â Â Â Âgpe_sts_write,
> + Â Â Â Â Â Â Â Â Â Â Â Â Âs);
> + Â Âregister_ioport_write(ACPI_GPE0_BLK_ADDRESS + ACPI_GPE0_BLK_LEN / 2,
> + Â Â Â Â Â Â Â Â Â Â Â Â ÂACPI_GPE0_BLK_LEN / 2,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â1,
> + Â Â Â Â Â Â Â Â Â Â Â Â Âgpe_en_write,
> + Â Â Â Â Â Â Â Â Â Â Â Â Âs);
> +
> + Â Âregister_savevm(NULL, "gpe", 0, 1, gpe_save, gpe_load, s);
> +}
> +
> +static int piix4_pm_xen_initfn(PCIDevice *dev)
> +{
> + Â ÂPCIAcpiState *s = DO_UPCAST(PCIAcpiState, dev, dev);
> + Â Âuint8_t *pci_conf;
> +
> + Â Âpci_conf = s->dev.config;
> + Â Âpci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
> + Â Âpci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
> + Â Âpci_conf[0x08] = 0x01; Â/* B0 stepping */
> + Â Âpci_conf[0x09] = 0x00; Â/* base class */
> + Â Âpci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
> + Â Âpci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */
> + Â Âpci_conf[0x3d] = 0x01; Â/* Hardwired to PIRQA is used */
> +
> + Â Â/* PMBA POWER MANAGEMENT BASE ADDRESS, hardcoded to 0x1f40
> + Â Â * to make shutdown work for IPF, due to IPF Guest Firmware
> + Â Â * will enumerate pci devices.
> + Â Â *
> + Â Â * TODO: Âif Guest Firmware or Guest OS will change this PMBA,
> + Â Â * More logic will be added.
> + Â Â */
> + Â Âpci_conf[0x40] = 0x41; /* Special device-specific BAR at 0x40 */
> + Â Âpci_conf[0x41] = 0x1f;
> + Â Âpci_conf[0x42] = 0x00;
> + Â Âpci_conf[0x43] = 0x00;
> +
> + Â Âs->pm1_control = ACPI_BITMASK_SCI_ENABLE;
> +
> + Â Âacpi_map((PCIDevice *)s, 0, 0x1f40, 0x10, PCI_BASE_ADDRESS_SPACE_IO);
> +
> + Â Âgpe_acpi_init();
> +
> + Â Âregister_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
> +
> + Â Âreturn 0;
> +}
> +
> +void piix4_pm_xen_init(PCIBus *bus, int devfn, qemu_irq sci_irq_spec, 
> qemu_irq cmos_s3)
> +{
> + Â ÂPCIDevice *dev;
> + Â ÂPCIAcpiState *s;
> +
> + Â Âsci_irq = sci_irq_spec;
> +
> + Â Âdev = pci_create(bus, devfn, "PIIX4 ACPI");
> +
> + Â Âs = DO_UPCAST(PCIAcpiState, dev, dev);
> +
> + Â Âs->irq = sci_irq_spec;
> + Â Âs->cmos_s3 = cmos_s3;
> +
> + Â Âqdev_init_nofail(&dev->qdev);
> +}
> +
> +static PCIDeviceInfo piix4_pm_xen_info = {
> +  Â.qdev.name  Â= "PIIX4 ACPI",
> +  Â.qdev.desc  Â= "dm",
> +  Â.qdev.size  Â= sizeof(PCIAcpiState),
> +  Â.qdev.vmsd  Â= &vmstate_acpi,
> +  Â.init     = piix4_pm_xen_initfn,
> +};
> +
> +static void piix4_pm_xen_register(void)
> +{
> + Â Âpci_qdev_register(&piix4_pm_xen_info);
> +}
> +
> +device_init(piix4_pm_xen_register);
> diff --git a/hw/xen_common.h b/hw/xen_common.h
> index 020fdd7..e1f07ba 100644
> --- a/hw/xen_common.h
> +++ b/hw/xen_common.h
> @@ -34,4 +34,7 @@
> Â/* hw/i8259-xen-stub.c */
> Âqemu_irq *i8259_xen_init(void);
>
> +/* hw/xen_acpi_piix4.c */
> +void piix4_pm_xen_init(PCIBus *bus, int devfn, qemu_irq sci_irq_spec, 
> qemu_irq cmos_s3);
> +
> Â#endif /* QEMU_HW_XEN_COMMON_H */
> diff --git a/hw/xen_machine_fv.c b/hw/xen_machine_fv.c
> index 77563db..bfda944 100644
> --- a/hw/xen_machine_fv.c
> +++ b/hw/xen_machine_fv.c
> @@ -92,7 +92,6 @@ static void xen_init_fv(ram_addr_t ram_size,
> Â Â qemu_irq *isa_irq;
> Â Â qemu_irq *i8259;
> Â Â qemu_irq *cmos_s3;
> - Â Âqemu_irq *smi_irq;
> Â Â IsaIrqState *isa_irq_state;
> Â Â DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
> Â Â FDCtrl *floppy_controller;
> @@ -208,10 +207,7 @@ static void xen_init_fv(ram_addr_t ram_size,
>
> Â Â if (acpi_enabled) {
> Â Â Â Â cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
> - Â Â Â Âsmi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
> - Â Â Â Âpiix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
> - Â Â Â Â Â Â Â Âisa_reserve_irq(9), *cmos_s3, *smi_irq,
> - Â Â Â Â Â Â Â Â0);
> + Â Â Â Âpiix4_pm_xen_init(pci_bus, piix3_devfn + 3, isa_reserve_irq(9), 
> *cmos_s3);
> Â Â }
>
> Â Â if (i440fx_state) {
> --
> 1.7.0.4
>
>
>

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