Hi all,
I just implement the EPT support in my hypervisor (Very similar to
Newbluepill). My new problem is irrelevant with Xen.
It's just about how to debug VTx implementation in drivers.
Here is the story. First, I implement a driver support partial VTx,
and it works very well. Then I implement EPT to identically map gfn to mfn from 0x0
to 0xfffff. I suppose it should be OK. But the result is the Windows
OS hangs (No reboot, No BSOD) when executing VMLAUNCH instruction.
And my problem is that, the windbg just shows "debuggee is running"
when the debuggee Windows OS hangs, even if I insert "ud2"
instruction before the next statement, #VMEXIT handler and the first
instruction in non-root mode. VMLAUNCH should not make this happen
according to Intel's manual 2B. Everything is OK if I set "enable
ept" to be 0 or clear the "EPT pointer" field in VMCS. Can someone
explain why this happens and what should I do to continue debugging?
Both the hypervisor and the Windows OS is on x86_32 platform. I use
windbg to debug the target machine via serial port.
Some debug information: EPT pointer is 0x9ba801e, (pfn:0x9ba8,
flag:0x1e, I have double checked this) PML4[0] =
0x00000000_09cd8007, PDPT[0] = 0x00000000_09cf3007, PD[0] =
0x00000000_09cf2007, PT[0] = 0x00000000_00000077. Other entries of
the same scheme with different values.
The debuggee is Intel i5 650, multi-core disabled.
Thanks,
Miao
On 11/17/2010 7:53 PM, Superymk wrote:
Thanks for Ian's answer. it comes to a more general scenario.
Hi Chu, EPT entry is 64 bit long, regardless the hypervisor is on
x86_32 platform or x86_64 platform. So there is no difference for
the hypervisor to use EPT on these two platforms.
On 11/17/2010 7:26 PM, Chu Rui wrote:
Okay, in my mind, the hardware has only one work mode,
32bit or 64bit. Thus the 32bit guest address will be extended
under the 64bit host.
But what will happen for a 64bit guest under a 32bit host
:-)
2010/11/17 Ian Campbell <Ian.Campbell@xxxxxxxxxx>
On Wed, 2010-11-17 at 10:32 +0000, George
Dunlap wrote:
> The exact implementation of 32-bit mode on a 64-bit
capable processor
> is something only the engineers at Intel know; but
logically yes,
> whatever it does is equivalent to first
zero-extending the 32-bit
> value.
Even on x86_32 physical addresses are >32 bit (think
PAE). cr3 is a
physical address, even if the register which exposes it
happens to be
limited to 32 bits. cr3 has probably already been expanded
to a full
physical address by the time EPT sees it and I don't think
there's any
difference between 32 and 64 bit (at least in this aspect)
in how EPT
handles the translation from physical address to machine
address.
Ian.
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