[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] RE: [Xen-devel] [PATCH][VTD] bug fix for EPT/VT-d table sharing
>>> On 07.01.11 at 03:49, "Kay, Allen M" <allen.m.kay@xxxxxxxxx> wrote: With this >@@ -548,17 +533,12 @@ static int inline iommu_flush_iotlb_psi( > if ( !cap_pgsel_inv(iommu->cap) ) > return iommu_flush_iotlb_dsi(iommu, did, flush_non_present_entry, > flush_dev_iotlb); > >- /* >- * PSI requires page size is 2 ^ x, and the base address is naturally >- * aligned to the size >- */ >- align = get_alignment(addr >> PAGE_SHIFT_4K, pages); > /* Fallback to domain selective flush if size is too big */ >- if ( align > cap_max_amask_val(iommu->cap) ) >+ if ( order > cap_max_amask_val(iommu->cap) ) > return iommu_flush_iotlb_dsi(iommu, did, flush_non_present_entry, > flush_dev_iotlb); > >- addr >>= PAGE_SHIFT_4K + align; >- addr <<= PAGE_SHIFT_4K + align; >+ addr >>= PAGE_SHIFT_4K + order; >+ addr <<= PAGE_SHIFT_4K + order; > > /* apply platform specific errata workarounds */ > vtd_ops_preamble_quirk(iommu); I suppose that here >@@ -635,7 +615,8 @@ static void dma_pte_clear_one(struct dom > if ( iommu_domid == -1 ) > continue; > if ( iommu_flush_iotlb_psi(iommu, iommu_domid, >- addr, 1, 0, flush_dev_iotlb) ) >+ addr, 1, PAGE_SHIFT_4K, >+ 0, flush_dev_iotlb) ) > iommu_flush_write_buffer(iommu); > } > } >@@ -1711,6 +1692,7 @@ static int intel_iommu_map_page( > continue; > if ( iommu_flush_iotlb_psi(iommu, iommu_domid, > (paddr_t)gfn << PAGE_SHIFT_4K, 1, >+ PAGE_SHIFT_4K, > !dma_pte_present(old), flush_dev_iotlb) ) > iommu_flush_write_buffer(iommu); > } you need to pass 0 instead of PAGE_SHIFT_4K. Jan _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
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