[Xen-devel] [PATCH] AMD IOMMU: Fix an interrupt remapping issue

[Wei Wang2 <wei.wang2@xxxxxxx>]

Some device could generate bogus interrupts if an IO-APIC RTE and an iommu 
interrupt remapping entry are not consistent during 2 adjacent 64bits IO-APIC 
RTE updates. For example, if the 2nd operation updates destination bits in 
RTE for SATA device and unmask it, in some case, SATA device will assert 
ioapic pin to generate interrupt immediately using new destination but iommu 
could still translate it into the old destination, then dom0 would be 
confused. To fix that, we sync up interrupt remapping entry with IO-APIC IRE 
on every 32 bits operation and foward IOAPIC RTE updates after interrupt 
remapping table has been changed. 

Jan, This patch fixes SATA device issue we observed (Bug #680824), please 
review it. Thanks! 
Wei
--
Advanced Micro Devices GmbH
Sitz: Dornach, Gemeinde Aschheim, 
Landkreis München Registergericht München, 
HRB Nr. 43632
WEEE-Reg-Nr: DE 12919551
Geschäftsführer:
Alberto Bozzo, Andrew Bowd


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