[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 20 of 20] n2 MSR handling and capability exposure
At 16:07 +0100 on 02 Jun (1307030872), Tim Deegan wrote: > At 16:57 +0800 on 02 Jun (1307033853), Eddie Dong wrote: > > + case MSR_IA32_VMX_PINBASED_CTLS: > > +#define REMOVED_PIN_CONTROL_CAP (PIN_BASED_PREEMPT_TIMER) > > + rdmsr(msr, eax, edx); > > + data = edx; > > + data = (data << 32) | eax; > > + break; > > You don't actually mask the value here. > > BTW, I don't really like defining all these REMOVED_* macros, each > of which is used only once a few lines from the definition (here and > elsewhere in the series). It just adds clutter for no benefit. > Oh, I forgot to say: will this feature-blacklisting work over live migration to a machine with a different CPU? There isn't an equivalnet of the CPUID masking feature to make all the machines in a cluster seem to have the same VMX features. Elsewhere we use whitelisting for passsing hardware capability flags to HVM guests; I think we should use whitelists here too. Cheers, Tim. > > + case MSR_IA32_VMX_PROCBASED_CTLS: > > + rdmsr(msr, eax, edx); > > +#define REMOVED_EXEC_CONTROL_CAP (CPU_BASED_TPR_SHADOW \ > > + | CPU_BASED_ACTIVATE_MSR_BITMAP \ > > + | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) > > + data = edx & ~REMOVED_EXEC_CONTROL_CAP; > > + data = (data << 32) | eax; > > + break; > > + case MSR_IA32_VMX_EXIT_CTLS: > > + rdmsr(msr, eax, edx); > > +#define REMOVED_EXIT_CONTROL_CAP (VM_EXIT_SAVE_GUEST_PAT \ > > + | VM_EXIT_LOAD_HOST_PAT \ > > + | VM_EXIT_SAVE_GUEST_EFER \ > > + | VM_EXIT_LOAD_HOST_EFER \ > > + | VM_EXIT_SAVE_PREEMPT_TIMER) > > + data = edx & ~REMOVED_EXIT_CONTROL_CAP; > > + data = (data << 32) | eax; > > + break; > > + case MSR_IA32_VMX_ENTRY_CTLS: > > + rdmsr(msr, eax, edx); > > +#define REMOVED_ENTRY_CONTROL_CAP (VM_ENTRY_LOAD_GUEST_PAT \ > > + | VM_ENTRY_LOAD_GUEST_EFER) > > + data = edx & ~REMOVED_ENTRY_CONTROL_CAP; > > + data = (data << 32) | eax; > > + break; > > + case MSR_IA32_VMX_PROCBASED_CTLS2: > > + mask = 0; > > + > > + rdmsr(msr, eax, edx); > > + data = edx & mask; > > + data = (data << 32) | eax; > > + break; > > + > -- Tim Deegan <Tim.Deegan@xxxxxxxxxx> Principal Software Engineer, Xen Platform Team Citrix Systems UK Ltd. (Company #02937203, SL9 0BG) _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel
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