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[Xen-devel] [PATCH] Add support for read-only APERF/MPERF

# HG changeset patch
# User Mark Langsdorf <mark.langsdorf@xxxxxxx>
# Date 1313072216 18000
# Node ID 9f048260512892889e9e8e5efa2150afa0910a75
# Parent  0f36c2eec2e1576b4db6538b5f22d625587c1a15
AMD is adding support for a read-only mode of the APERF
and MPERF MSRs. When this mode is enabled, writes to
these registers are ignored and do no reset the registers.
This allows multiple well-behaved programs to share the
use of the registers even if a poorly behaved program
attempts to reset them. Support for this feature is
indicated by a CPUID bit.

AMD has been recommending that well-behaved software
avoid resetting the APERF and MPERF MSRs. Enabling
this feature should not change the behavior of well-
behaved software. This change has been tested with the
turbostat and cpufreq-aperf applications.

Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxx>

diff -r 0f36c2eec2e1 -r 9f0482605128 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c    Thu Jul 28 15:40:54 2011 +0100
+++ b/xen/arch/x86/cpu/amd.c    Thu Aug 11 09:16:56 2011 -0500
@@ -499,6 +499,12 @@
        if (c->x86 > 0xf && !cpu_has_amd_erratum(c, AMD_ERRATUM_400))
                set_bit(X86_FEATURE_ARAT, c->x86_capability);
+       if (cpuid_edx(0x80000007) & (1 << 10)) {
+               rdmsr(MSR_K7_HWCR, l, h);
+               l |= (1 << 27); /* Enable read-only APERF/MPERF bit */
+               wrmsr(MSR_K7_HWCR, l, h);
+       }
        /* Prevent TSC drift in non single-processor, single-core platforms. */
        if ((smp_processor_id() == 1) && c1_ramping_may_cause_clock_drift(c))

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