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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH] x86: remove redundant MCE related MSR definitions
On 12/12/2011 15:35, "Jan Beulich" <JBeulich@xxxxxxxx> wrote:
> Two definitions (the first register and a macro to calculate the
> register for a given bank) are sufficient per kind of register.
>
> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Keir Fraser <keir@xxxxxxx>
> --- 2011-11-23.orig/xen/arch/x86/cpu/mcheck/amd_nonfatal.c 2011-12-05
> 11:38:33.000000000 +0100
> +++ 2011-11-23/xen/arch/x86/cpu/mcheck/amd_nonfatal.c 2011-12-05
> 11:24:15.000000000 +0100
> @@ -144,7 +144,7 @@ static void mce_amd_work_fn(void *data)
> uint64_t value;
> uint32_t counter;
>
> - value = mca_rdmsr(MSR_IA32_MC4_MISC);
> + value = mca_rdmsr(MSR_IA32_MCx_MISC(4));
> /* Only the error counter field is of interest
> * Bit field is described in AMD K8 BKDG chapter 6.4.5.5
> */
> @@ -174,7 +174,7 @@ static void mce_amd_work_fn(void *data)
> value &= ~(0x60FFF00000000ULL);
> /* Counter enable */
> value |= (1ULL << 51);
> - mca_wrmsr(MSR_IA32_MC4_MISC, value);
> + mca_wrmsr(MSR_IA32_MCx_MISC(4), value);
> wmb();
> }
> }
> @@ -217,7 +217,7 @@ void amd_nonfatal_mcheck_init(struct cpu
>
> /* hw threshold registers present */
> hw_threshold = 1;
> - rdmsrl(MSR_IA32_MC4_MISC, value);
> + rdmsrl(MSR_IA32_MCx_MISC(4), value);
>
> if (value & (1ULL << 61)) { /* Locked bit */
> /* Locked by BIOS. Not available for use */
> @@ -238,7 +238,7 @@ void amd_nonfatal_mcheck_init(struct cpu
> value &= ~(0x60FFF00000000ULL);
> /* Counter enable */
> value |= (1ULL << 51);
> - wrmsrl(MSR_IA32_MC4_MISC, value);
> + wrmsrl(MSR_IA32_MCx_MISC(4), value);
> /* serialize */
> wmb();
> printk(XENLOG_INFO "MCA: Use hw thresholding to adjust polling frequency\n");
> --- 2011-11-23.orig/xen/arch/x86/cpu/mcheck/mce_amd_quirks.c 2011-12-05
> 11:41:00.000000000 +0100
> +++ 2011-11-23/xen/arch/x86/cpu/mcheck/mce_amd_quirks.c 2011-12-05
> 11:42:03.000000000 +0100
> @@ -68,8 +68,8 @@ int mcequirk_amd_apply(enum mcequirk_amd
> * TBL walk error reporting, which trips off incorrectly
> * with AGP GART & 3ware & Cerberus.
> */
> - wrmsrl(MSR_IA32_MC4_CTL, ~(1ULL << 10));
> - wrmsrl(MSR_IA32_MC4_STATUS, 0ULL);
> + wrmsrl(MSR_IA32_MCx_CTL(4), ~(1ULL << 10));
> + wrmsrl(MSR_IA32_MCx_STATUS(4), 0ULL);
> break;
> case MCEQUIRK_F10_GART:
> if (rdmsr_safe(MSR_AMD64_MCx_MASK(4), val) == 0)
> --- 2011-11-23.orig/xen/arch/x86/cpu/mcheck/mce_intel.c 2011-12-05
> 11:38:33.000000000 +0100
> +++ 2011-11-23/xen/arch/x86/cpu/mcheck/mce_intel.c 2011-12-05
> 11:27:53.000000000 +0100
> @@ -986,7 +986,7 @@ static DEFINE_SPINLOCK(cmci_discover_loc
> */
> static int do_cmci_discover(int i)
> {
> - unsigned msr = MSR_IA32_MC0_CTL2 + i;
> + unsigned msr = MSR_IA32_MCx_CTL2(i);
> u64 val;
>
> rdmsrl(msr, val);
> @@ -1095,7 +1095,7 @@ static void clear_cmci(void)
> smp_processor_id());
>
> for (i = 0; i < nr_mce_banks; i++) {
> - unsigned msr = MSR_IA32_MC0_CTL2 + i;
> + unsigned msr = MSR_IA32_MCx_CTL2(i);
> u64 val;
> if (!mcabanks_test(i, __get_cpu_var(mce_banks_owned)))
> continue;
> --- 2011-11-23.orig/xen/arch/x86/hvm/svm/svm.c 2011-12-05 11:38:33.000000000
> +0100
> +++ 2011-11-23/xen/arch/x86/hvm/svm/svm.c 2011-12-05 11:25:55.000000000 +0100
> @@ -1318,7 +1318,7 @@ static int svm_msr_read_intercept(unsign
> *msr_content = v->arch.hvm_svm.guest_sysenter_eip;
> break;
>
> - case MSR_IA32_MC4_MISC: /* Threshold register */
> + case MSR_IA32_MCx_MISC(4): /* Threshold register */
> case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
> /*
> * MCA/MCE: We report that the threshold register is unavailable
> @@ -1498,7 +1498,7 @@ static int svm_msr_write_intercept(unsig
> vpmu_do_wrmsr(msr, msr_content);
> break;
>
> - case MSR_IA32_MC4_MISC: /* Threshold register */
> + case MSR_IA32_MCx_MISC(4): /* Threshold register */
> case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
> /*
> * MCA/MCE: Threshold register is reported to be locked, so we ignore
> --- 2011-11-23.orig/xen/include/asm-x86/msr-index.h 2011-12-05
> 11:06:39.000000000 +0100
> +++ 2011-11-23/xen/include/asm-x86/msr-index.h 2011-12-05 11:21:46.000000000
> +0100
> @@ -100,58 +100,11 @@
>
> #define MSR_AMD64_MC0_MASK 0xc0010044
>
> -#define MSR_IA32_MC1_CTL 0x00000404
> -#define MSR_IA32_MC1_CTL2 0x00000281
> -#define MSR_IA32_MC1_STATUS 0x00000405
> -#define MSR_IA32_MC1_ADDR 0x00000406
> -#define MSR_IA32_MC1_MISC 0x00000407
> -
> -#define MSR_IA32_MC2_CTL 0x00000408
> -#define MSR_IA32_MC2_CTL2 0x00000282
> -#define MSR_IA32_MC2_STATUS 0x00000409
> -#define MSR_IA32_MC2_ADDR 0x0000040A
> -#define MSR_IA32_MC2_MISC 0x0000040B
> -
> -#define MSR_IA32_MC3_CTL2 0x00000283
> -#define MSR_IA32_MC3_CTL 0x0000040C
> -#define MSR_IA32_MC3_STATUS 0x0000040D
> -#define MSR_IA32_MC3_ADDR 0x0000040E
> -#define MSR_IA32_MC3_MISC 0x0000040F
> -
> -#define MSR_IA32_MC4_CTL2 0x00000284
> -#define MSR_IA32_MC4_CTL 0x00000410
> -#define MSR_IA32_MC4_STATUS 0x00000411
> -#define MSR_IA32_MC4_ADDR 0x00000412
> -#define MSR_IA32_MC4_MISC 0x00000413
> -
> -#define MSR_IA32_MC5_CTL2 0x00000285
> -#define MSR_IA32_MC5_CTL 0x00000414
> -#define MSR_IA32_MC5_STATUS 0x00000415
> -#define MSR_IA32_MC5_ADDR 0x00000416
> -#define MSR_IA32_MC5_MISC 0x00000417
> -
> -#define MSR_IA32_MC6_CTL2 0x00000286
> -#define MSR_IA32_MC6_CTL 0x00000418
> -#define MSR_IA32_MC6_STATUS 0x00000419
> -#define MSR_IA32_MC6_ADDR 0x0000041A
> -#define MSR_IA32_MC6_MISC 0x0000041B
> -
> -#define MSR_IA32_MC7_CTL2 0x00000287
> -#define MSR_IA32_MC7_CTL 0x0000041C
> -#define MSR_IA32_MC7_STATUS 0x0000041D
> -#define MSR_IA32_MC7_ADDR 0x0000041E
> -#define MSR_IA32_MC7_MISC 0x0000041F
> -
> -#define MSR_IA32_MC8_CTL2 0x00000288
> -#define MSR_IA32_MC8_CTL 0x00000420
> -#define MSR_IA32_MC8_STATUS 0x00000421
> -#define MSR_IA32_MC8_ADDR 0x00000422
> -#define MSR_IA32_MC8_MISC 0x00000423
> -
> #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
> #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
> #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
> #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
> +#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
>
> #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
>
>
>
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