[Xen-devel] [PATCH 2 of 9] arm: Add a comment explaining the GICD writes in the GICC init function

[Tim Deegan <tim@xxxxxxx>]

# HG changeset patch
# User Tim Deegan <tim@xxxxxxx>
# Date 1331300346 0
# Node ID 51da35a2e502779efb78402013da38a1960a6129
# Parent  7a00e582027ed2793f4ee393f94ddf790b61c39f
arm: Add a comment explaining the GICD writes in the GICC init function.

Signed-off-by: Tim Deegan <tim@xxxxxxx>

diff -r 7a00e582027e -r 51da35a2e502 xen/arch/arm/gic.c
--- a/xen/arch/arm/gic.c        Fri Mar 09 13:39:06 2012 +0000
+++ b/xen/arch/arm/gic.c        Fri Mar 09 13:39:06 2012 +0000
@@ -224,7 +224,9 @@ static void __cpuinit gic_cpu_init(void)
 {
     int i;
 
-    /* Disable all PPI and enable all SGI */
+    /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so 
+     * even though they are controlled with GICD registers, they must 
+     * be set up here with the other per-cpu state. */
     GICD[GICD_ICENABLER] = 0xffff0000; /* Disable all PPI */
     GICD[GICD_ISENABLER] = 0x0000ffff; /* Enable all SGI */
     /* Set PPI and SGI priorities */

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