Re: [Xen-devel] LWP Interrupt Handler

["Zhang, Xiantao" <xiantao.zhang@xxxxxxxxx>]

Please make sure the per-cpu vector is considered in your case.  For CPU's 
built-in event, it always happens on all cpus,  but IRQ-based events may only 
happen on some special cpus which are determined by apic's mode.  
Xiantao

> -----Original Message-----
> From: xen-devel-bounces@xxxxxxxxxxxxx [mailto:xen-devel-
> bounces@xxxxxxxxxxxxx] On Behalf Of Keir Fraser
> Sent: Saturday, March 24, 2012 6:50 AM
> To: wei.huang2@xxxxxxx; xen-devel@xxxxxxxxxxxxx; Jan Beulich
> Subject: Re: [Xen-devel] LWP Interrupt Handler
> 
> On 23/03/2012 22:03, "Wei Huang" <wei.huang2@xxxxxxx> wrote:
> 
> > I am adding interrupt support for LWP, whose spec is available at
> > http://support.amd.com/us/Processor_TechDocs/43724.pdf. Basically OS
> > can specify an interrupt vector in LWP_CFG MSR; the interrupt will be
> > triggered when event buffer overflows. For HVM guests, I want to
> > re-inject this interrupt back into the guest VM. Here is one idea
> > similar to virtualized PMU: It first registers a special interrupt
> > handler (say on vector 0xf6) using set_intr_gate(). When triggered,
> > this handler injects an IRQ (with vector copied from LWP_CFG) into
> > guest VM via virtual local APIC. This worked from my test.
> >
> > But adding a interrupt handler seems to be an overkill. Is there any
> > better way to create a dummy interrupt receiver on be-behalf of guest
> > VMs? I also looked into IRQ and MSI solutions inside Xen. But most of
> > them assume that interrupts are from physical device (but not in this
> > LWP case, where interrupt is initiated from CPU itself); so they don't
> > fit very well.
> 
> I think just allocating a vector is fine. If we get too many we could move to
> dynamic allocation of them.
> 
>  -- Keir
> 
> > Thanks,
> > -Wei
> >
> >
> 
> 
> 
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