Re: [Xen-devel] [PATCH 29/38] arm: delay enabling data-cache until paging enabled.

[Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>]

On Fri, 1 Jun 2012, Ian Campbell wrote:
> cached before paging was enabled had been mapped with to inconsistent sets of
> attributes. I'm not convinced that isn't a model issue, nor am I convinced
> this has really fixed anything, but it seems sensible enough.
> 
> Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
> ---
>  xen/arch/arm/head.S |    9 +++++++--
>  1 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/arch/arm/head.S b/xen/arch/arm/head.S
> index 9a7714a..71197af 100644
> --- a/xen/arch/arm/head.S
> +++ b/xen/arch/arm/head.S
> @@ -148,10 +148,11 @@ hyp:
>        * Exceptions in LE ARM,
>        * Low-latency IRQs disabled,
>        * Write-implies-XN disabled (for now),
> -      * I-cache and d-cache enabled,
> +      * D-cache diabled (for now),
                 ^ misspell
> +      * I-cache enabled,
>        * Alignment checking enabled,
>        * MMU translation disabled (for now). */
> -     ldr   r0, =(HSCTLR_BASE|SCTLR_A|SCTLR_C)
> +     ldr   r0, =(HSCTLR_BASE|SCTLR_A)
>       mcr   CP32(r0, HSCTLR)
>  
>       /* Write Xen's PT's paddr into the HTTBR */
> @@ -217,6 +218,10 @@ pt_ready:
>       mov   pc, r1                 /* Get a proper vaddr into PC */
>  paging:
>  
> +     mrc   CP32(r0, HSCTLR)       /* Now enable data cache */
> +     orr   r0, r0, #(SCTLR_C)
> +     mcr   CP32(r0, HSCTLR)
> +
>  #ifdef EARLY_UART_ADDRESS
>       /* Recover the UART address in the new address space. */
>       lsl   r11, #11
> -- 
> 1.7.9.1
> 
> 
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> 

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