Re: [Xen-devel] [PATCH 1/4] arm: disable distributor delivery on boot CPU only

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Mon, 2012-08-06 at 12:56 +0100, Ian Campbell wrote:
> On Mon, 2012-08-06 at 12:55 +0100, Tim Deegan wrote:
> > At 11:34 +0000 on 06 Aug (1344252897), Ian Campbell wrote:
> > > The secondary processors do not call enter_hyp_mode until the boot CPU
> > > has brought most of the system up, including enabling delivery via the
> > > distributor. This means that bringing up secondary CPUs unexpectedly
> > > disables the GICD again, meaning we get no further interrupts on any
> > > CPU.
> > > 
> > > It's not clear that the distributor actually needs to be disabled to
> > > modify the group registers but it seems reasonable that the bringup
> > > code should make sure the GICD is disabled even if not doing the
> > > transition to hyp mode, so move this to the main flow of head.S and
> > > only do it on the boot processor.
> > > 
> > > For completeness also disable the GICC (CPU interface) on all CPUs
> > > too.
> > 
> > I think that having interrupts disabled is something we can rely on the
> > bootloader/firmware handling for us, so this should all stay in
> > mode_switch.S for now, and avoid leaking GIC_* magic constants into
> > head.S.  (Unless you fancy writing a DT parser in assembler :))
> 
> Not really ;-) I'll move this back then.

8<---------------------------------------------------------------

>From 6440d1868cb03573ebacf5eb3cfc69f4f6abdf15 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ian.campbell@xxxxxxxxxx>
Date: Mon, 6 Aug 2012 09:40:59 +0000
Subject: [PATCH] arm: disable distributor delivery on boot CPU only

The secondary processors do not call enter_hyp_mode until the boot CPU
has brought most of the system up, including enabling delivery via the
distributor. This means that bringing up secondary CPUs unexpectedly
disables the GICD again, meaning we get no further interrupts on any
CPU.

For completeness also disable the GICC (CPU interface) on all CPUs
too.

Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
 xen/arch/arm/mode_switch.S |   23 +++++++++++++++++------
 1 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/xen/arch/arm/mode_switch.S b/xen/arch/arm/mode_switch.S
index f5549d7..acbd523 100644
--- a/xen/arch/arm/mode_switch.S
+++ b/xen/arch/arm/mode_switch.S
@@ -23,6 +23,8 @@
 
 /* Get up a CPU into Hyp mode.  Clobbers r0-r3.
  *
+ * Expects r12 == CPU number
+ *
  * This code is specific to the VE model, and not intended to be used
  * on production systems.  As such it's a bit hackier than the main
  * boot code in head.S.  In future it will be replaced by better
@@ -46,19 +48,28 @@ enter_hyp_mode:
        mcr   CP32(r0, CNTFRQ)
        ldr   r0, =0x40c00           /* SMP, c11, c10 in non-secure mode */
        mcr   CP32(r0, NSACR)
-       /* Continuing ugliness: Set up the GIC so NS state owns interrupts */
        mov   r0, #GIC_BASE_ADDRESS
        add   r0, r0, #GIC_DR_OFFSET
+       /* Disable the GIC distributor, on the boot CPU only */
        mov   r1, #0
-       str   r1, [r0]               /* Disable delivery in the distributor */
+       teq   r12, #0                /* Is this the boot CPU? */
+       streq r1, [r0]
+       /* Continuing ugliness: Set up the GIC so NS state owns interrupts,
+        * The first 32 interrupts (SGIs & PPIs) must be configured on all
+        * CPUs while the remainder are SPIs and only need to be done one, on
+        * the boot CPU. */
        add   r0, r0, #0x80          /* GICD_IGROUP0 */
        mov   r2, #0xffffffff        /* All interrupts to group 1 */
-       str   r2, [r0]
-       str   r2, [r0, #4]
-       str   r2, [r0, #8]
-       /* Must drop priority mask below 0x80 before entering NS state */
+       teq   r12, #0                /* Boot CPU? */
+       str   r2, [r0]               /* Interrupts  0-31 (SGI & PPI) */
+       streq r2, [r0, #4]           /* Interrupts 32-63 (SPI) */
+       streq r2, [r0, #8]           /* Interrupts 64-95 (SPI) */
+       /* Disable the GIC CPU interface on all processors */
        mov   r0, #GIC_BASE_ADDRESS
        add   r0, r0, #GIC_CR_OFFSET
+       mov   r1, #0
+       str   r1, [r0]               
+       /* Must drop priority mask below 0x80 before entering NS state */
        ldr   r1, =0xff
        str   r1, [r0, #0x4]         /* -> GICC_PMR */
        /* Reset a few config registers */
-- 
1.7.9.1




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