[Xen-devel] [PATCH] x86: remove further code applicable to 32-bit CPUs only

["Jan Beulich" <JBeulich@xxxxxxxx>]

On the AMD side, anything prior to family 0xf can now be ignored, as
well as very low model numbers of family 6 on the Intel side.

Apart from that, there were several made up CPU features that turned
out entirely unused throughout the tree.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -180,7 +180,7 @@ static void __devinit set_cpuidmask(cons
        if (c->x86 >= 0x10) {
                wrmsr(MSR_K8_FEATURE_MASK, feat_edx, feat_ecx);
                wrmsr(MSR_K8_EXT_FEATURE_MASK, extfeat_edx, extfeat_ecx);
-       } else if (c->x86 == 0x0f) {
+       } else {
                wrmsr_amd(MSR_K8_FEATURE_MASK, feat_edx, feat_ecx);
                wrmsr_amd(MSR_K8_EXT_FEATURE_MASK, extfeat_edx, extfeat_ecx);
        }
@@ -234,14 +234,7 @@ int cpu_has_amd_erratum(const struct cpu
 /* Can this system suffer from TSC drift due to C1 clock ramping? */
 static int c1_ramping_may_cause_clock_drift(struct cpuinfo_x86 *c) 
 { 
-       if (c->x86 < 0xf) {
-               /*
-                * TSC drift doesn't exist on 7th Gen or less
-                * However, OS still needs to consider effects
-                * of P-state changes on TSC
-                */
-               return 0;
-       } else if (cpuid_edx(0x80000007) & (1<<8)) {
+       if (cpuid_edx(0x80000007) & (1<<8)) {
                /*
                 * CPUID.AdvPowerMgmtInfo.TscInvariant
                 * EDX bit 8, 8000_0007
@@ -416,41 +409,7 @@ static void __devinit init_amd(struct cp
 
        switch(c->x86)
        {
-       case 6: /* An Athlon/Duron */
- 
-               /* Bit 15 of Athlon specific MSR 15, needs to be 0
-                * to enable SSE on Palomino/Morgan/Barton CPU's.
-                * If the BIOS didn't enable it already, enable it here.
-                */
-               if (c->x86_model >= 6 && c->x86_model <= 10) {
-                       if (!cpu_has(c, X86_FEATURE_XMM)) {
-                               printk(KERN_INFO "Enabling disabled K7/SSE 
Support.\n");
-                               rdmsr(MSR_K7_HWCR, l, h);
-                               l &= ~0x00008000;
-                               wrmsr(MSR_K7_HWCR, l, h);
-                               set_bit(X86_FEATURE_XMM, c->x86_capability);
-                       }
-               }
-
-               /* It's been determined by AMD that Athlons since model 8 
stepping 1
-                * are more robust with CLK_CTL set to 200xxxxx instead of 
600xxxxx
-                * As per AMD technical note 27212 0.2
-                */
-               if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 
8)) {
-                       rdmsr(MSR_K7_CLK_CTL, l, h);
-                       if ((l & 0xfff00000) != 0x20000000) {
-                               printk ("CPU: CLK_CTL MSR was %x. Reprogramming 
to %x\n", l,
-                                       ((l & 0x000fffff)|0x20000000));
-                               wrmsr(MSR_K7_CLK_CTL, (l & 
0x000fffff)|0x20000000, h);
-                       }
-               }
-               set_bit(X86_FEATURE_K7, c->x86_capability);
-               break;
-
-       case 0xf:
-       /* Use K8 tuning for Fam10h and Fam11h */
-       case 0x10 ... 0x17:
-               set_bit(X86_FEATURE_K8, c->x86_capability);
+       case 0xf ... 0x17:
                disable_c1e(NULL);
                if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
                        pv_post_outb_hook = check_disable_c1e;
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -192,7 +192,6 @@ static int __devinit num_cpu_cores(struc
 static void __devinit init_intel(struct cpuinfo_x86 *c)
 {
        unsigned int l2 = 0;
-       char *p = NULL;
 
        /* Detect the extended topology information if available */
        detect_extended_topology(c);
@@ -210,37 +209,6 @@ static void __devinit init_intel(struct 
        if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
                clear_bit(X86_FEATURE_SEP, c->x86_capability);
 
-       /* Names for the Pentium II/Celeron processors 
-          detectable only by also checking the cache size.
-          Dixon is NOT a Celeron. */
-       if (c->x86 == 6) {
-               switch (c->x86_model) {
-               case 5:
-                       if (c->x86_mask == 0) {
-                               if (l2 == 0)
-                                       p = "Celeron (Covington)";
-                               else if (l2 == 256)
-                                       p = "Mobile Pentium II (Dixon)";
-                       }
-                       break;
-                       
-               case 6:
-                       if (l2 == 128)
-                               p = "Celeron (Mendocino)";
-                       else if (c->x86_mask == 0 || c->x86_mask == 5)
-                               p = "Celeron-A";
-                       break;
-                       
-               case 8:
-                       if (l2 == 128)
-                               p = "Celeron (Coppermine)";
-                       break;
-               }
-       }
-
-       if ( p )
-               safe_strcpy(c->x86_model_id, p);
-
        if ( !cpu_has(c, X86_FEATURE_XTOPOLOGY) )
        {
                c->x86_max_cores = num_cpu_cores(c);
@@ -275,10 +243,6 @@ static void __devinit init_intel(struct 
        }
 #endif
 
-       if (c->x86 == 15)
-               set_bit(X86_FEATURE_P4, c->x86_capability);
-       if (c->x86 == 6) 
-               set_bit(X86_FEATURE_P3, c->x86_capability);
        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
                (c->x86 == 0x6 && c->x86_model >= 0x0e))
                set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -64,15 +64,6 @@
 
 /* Other features, Linux-defined mapping, word 3 */
 /* This range is used for feature bits which conflict or are synthesized */
-#define X86_FEATURE_CXMMX      (3*32+ 0) /* Cyrix MMX extensions */
-#define X86_FEATURE_K6_MTRR    (3*32+ 1) /* AMD K6 nonstandard MTRRs */
-#define X86_FEATURE_CYRIX_ARR  (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
-#define X86_FEATURE_CENTAUR_MCR        (3*32+ 3) /* Centaur MCRs (= MTRRs) */
-/* cpu types for specific tunings: */
-#define X86_FEATURE_K8         (3*32+ 4) /* Opteron, Athlon64 */
-#define X86_FEATURE_K7         (3*32+ 5) /* Athlon */
-#define X86_FEATURE_P3         (3*32+ 6) /* P3 */
-#define X86_FEATURE_P4         (3*32+ 7) /* P4 */
 #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
 #define X86_FEATURE_NONSTOP_TSC        (3*32+ 9) /* TSC does not stop in C 
states */
 #define X86_FEATURE_ARAT       (3*32+ 10) /* Always running APIC timer */

Attachment: x86-no-PIII.patch
Description: Text document

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