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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 1/3] trace: allow for different sub-classes of TRC_PV_* tracepoints
On Mon, Oct 1, 2012 at 6:47 PM, David Vrabel <david.vrabel@xxxxxxxxxx> wrote:
> From: David Vrabel <david.vrabel@xxxxxxxxxx>
>
> We want to add additional sub-classes for TRC_PV tracepoints and to be
> able to only capture these new sub-classes. This cannot currently be
> done as the existing tracepoints all use a sub-class of 0xf.
>
> So, redefine the PV events to use a new sub-class. All the current
> tracepoints are tracing entry points to the hypervisor so the
> sub-class is named TRC_PV_ENTRY.
>
> This change does not affect xenalyze as that only looks at the main
> class and the event number and does not use the sub-class field.
>
> Signed-off-by: Frediano Ziglio <frediano.ziglio@xxxxxxxxxx>
> Signed-off-by: David Vrabel <david.vrabel@xxxxxxxxxx>
> Acked-by: George Dunlap <george.dunlap@xxxxxxxxxx>
Ack re-confirmed.
> ---
> tools/xentrace/formats | 44
> ++++++++++++++++++++++----------------------
> xen/include/public/trace.h | 35 +++++++++++++++++++++--------------
> 2 files changed, 43 insertions(+), 36 deletions(-)
>
> diff --git a/tools/xentrace/formats b/tools/xentrace/formats
> index 04e54d5..71220c0 100644
> --- a/tools/xentrace/formats
> +++ b/tools/xentrace/formats
> @@ -82,28 +82,28 @@
> 0x0010f002 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_grant_unmap [ domid
> = %(1)d ]
> 0x0010f003 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_grant_transfer [ domid
> = %(1)d ]
>
> -0x0020f001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) hypercall [ eip =
> 0x%(1)08x, eax = 0x%(2)08x ]
> -0x0020f101 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) hypercall [ rip =
> 0x%(2)08x%(1)08x, eax = 0x%(3)08x ]
> -0x0020f003 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) trap [ eip =
> 0x%(1)08x, trapnr:error = 0x%(2)08x ]
> -0x0020f103 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) trap [ rip =
> 0x%(2)08x%(1)08x, trapnr:error = 0x%(3)08x ]
> -0x0020f004 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_fault [ eip =
> 0x%(1)08x, addr = 0x%(2)08x, error = 0x%(3)08x ]
> -0x0020f104 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_fault [ rip =
> 0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x, error = 0x%(5)08x ]
> -0x0020f005 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) forced_invalid_op [ eip =
> 0x%(1)08x ]
> -0x0020f105 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) forced_invalid_op [ rip =
> 0x%(2)08x%(1)08x ]
> -0x0020f006 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_privop [ eip =
> 0x%(1)08x ]
> -0x0020f106 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_privop [ rip =
> 0x%(2)08x%(1)08x ]
> -0x0020f007 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_4G [ eip =
> 0x%(1)08x ]
> -0x0020f107 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_4G [ rip =
> 0x%(2)08x%(1)08x ]
> -0x0020f008 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) math_state_restore
> -0x0020f108 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) math_state_restore
> -0x0020f009 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) paging_fixup [ eip =
> 0x%(1)08x, addr = 0x%(2)08x ]
> -0x0020f109 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) paging_fixup [ rip =
> 0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x ]
> -0x0020f00a CPU%(cpu)d %(tsc)d (+%(reltsc)8d) gdt_ldt_mapping_fault [ eip
> = 0x%(1)08x, offset = 0x%(2)08x ]
> -0x0020f10a CPU%(cpu)d %(tsc)d (+%(reltsc)8d) gdt_ldt_mapping_fault [ rip
> = 0x%(2)08x%(1)08x, offset = 0x%(4)08x%(3)08x ]
> -0x0020f00b CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation [ addr =
> 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
> -0x0020f10b CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation [ addr =
> 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
> -0x0020f00c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation_pae [ addr =
> 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
> -0x0020f10c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation_pae [ addr =
> 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
> +0x00201001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) hypercall [ eip =
> 0x%(1)08x, eax = 0x%(2)08x ]
> +0x00201101 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) hypercall [ rip =
> 0x%(2)08x%(1)08x, eax = 0x%(3)08x ]
> +0x00201003 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) trap [ eip =
> 0x%(1)08x, trapnr:error = 0x%(2)08x ]
> +0x00201103 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) trap [ rip =
> 0x%(2)08x%(1)08x, trapnr:error = 0x%(3)08x ]
> +0x00201004 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_fault [ eip =
> 0x%(1)08x, addr = 0x%(2)08x, error = 0x%(3)08x ]
> +0x00201104 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_fault [ rip =
> 0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x, error = 0x%(5)08x ]
> +0x00201005 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) forced_invalid_op [ eip =
> 0x%(1)08x ]
> +0x00201105 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) forced_invalid_op [ rip =
> 0x%(2)08x%(1)08x ]
> +0x00201006 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_privop [ eip =
> 0x%(1)08x ]
> +0x00201106 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_privop [ rip =
> 0x%(2)08x%(1)08x ]
> +0x00201007 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_4G [ eip =
> 0x%(1)08x ]
> +0x00201107 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_4G [ rip =
> 0x%(2)08x%(1)08x ]
> +0x00201008 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) math_state_restore
> +0x00201108 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) math_state_restore
> +0x00201009 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) paging_fixup [ eip =
> 0x%(1)08x, addr = 0x%(2)08x ]
> +0x00201109 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) paging_fixup [ rip =
> 0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x ]
> +0x0020100a CPU%(cpu)d %(tsc)d (+%(reltsc)8d) gdt_ldt_mapping_fault [ eip
> = 0x%(1)08x, offset = 0x%(2)08x ]
> +0x0020110a CPU%(cpu)d %(tsc)d (+%(reltsc)8d) gdt_ldt_mapping_fault [ rip
> = 0x%(2)08x%(1)08x, offset = 0x%(4)08x%(3)08x ]
> +0x0020100b CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation [ addr =
> 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
> +0x0020110b CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation [ addr =
> 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
> +0x0020100c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation_pae [ addr =
> 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
> +0x0020110c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation_pae [ addr =
> 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
>
> 0x0040f001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_not_shadow
> [ gl1e = 0x%(2)08x%(1)08x, va = 0x%(3)08x, flags = 0x%(4)08x ]
> 0x0040f101 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_not_shadow
> [ gl1e = 0x%(2)08x%(1)08x, va = 0x%(4)08x%(3)08x, flags = 0x%(5)08x ]
> diff --git a/xen/include/public/trace.h b/xen/include/public/trace.h
> index 0dfabe9..1f154bb 100644
> --- a/xen/include/public/trace.h
> +++ b/xen/include/public/trace.h
> @@ -94,20 +94,19 @@
> #define TRC_MEM_POD_ZERO_RECLAIM (TRC_MEM + 17)
> #define TRC_MEM_POD_SUPERPAGE_SPLINTER (TRC_MEM + 18)
>
> -
> -#define TRC_PV_HYPERCALL (TRC_PV + 1)
> -#define TRC_PV_TRAP (TRC_PV + 3)
> -#define TRC_PV_PAGE_FAULT (TRC_PV + 4)
> -#define TRC_PV_FORCED_INVALID_OP (TRC_PV + 5)
> -#define TRC_PV_EMULATE_PRIVOP (TRC_PV + 6)
> -#define TRC_PV_EMULATE_4GB (TRC_PV + 7)
> -#define TRC_PV_MATH_STATE_RESTORE (TRC_PV + 8)
> -#define TRC_PV_PAGING_FIXUP (TRC_PV + 9)
> -#define TRC_PV_GDT_LDT_MAPPING_FAULT (TRC_PV + 10)
> -#define TRC_PV_PTWR_EMULATION (TRC_PV + 11)
> -#define TRC_PV_PTWR_EMULATION_PAE (TRC_PV + 12)
> - /* Indicates that addresses in trace record are 64 bits */
> -#define TRC_64_FLAG (0x100)
> +#define TRC_PV_ENTRY 0x00201000 /* Hypervisor entry points for PV guests. */
> +
> +#define TRC_PV_HYPERCALL (TRC_PV_ENTRY + 1)
> +#define TRC_PV_TRAP (TRC_PV_ENTRY + 3)
> +#define TRC_PV_PAGE_FAULT (TRC_PV_ENTRY + 4)
> +#define TRC_PV_FORCED_INVALID_OP (TRC_PV_ENTRY + 5)
> +#define TRC_PV_EMULATE_PRIVOP (TRC_PV_ENTRY + 6)
> +#define TRC_PV_EMULATE_4GB (TRC_PV_ENTRY + 7)
> +#define TRC_PV_MATH_STATE_RESTORE (TRC_PV_ENTRY + 8)
> +#define TRC_PV_PAGING_FIXUP (TRC_PV_ENTRY + 9)
> +#define TRC_PV_GDT_LDT_MAPPING_FAULT (TRC_PV_ENTRY + 10)
> +#define TRC_PV_PTWR_EMULATION (TRC_PV_ENTRY + 11)
> +#define TRC_PV_PTWR_EMULATION_PAE (TRC_PV_ENTRY + 12)
>
> #define TRC_SHADOW_NOT_SHADOW (TRC_SHADOW + 1)
> #define TRC_SHADOW_FAST_PROPAGATE (TRC_SHADOW + 2)
> @@ -187,6 +186,14 @@
> #define TRC_HW_IRQ_UNMAPPED_VECTOR (TRC_HW_IRQ + 0x7)
> #define TRC_HW_IRQ_HANDLED (TRC_HW_IRQ + 0x8)
>
> +/*
> + * Event Flags
> + *
> + * Some events (e.g, TRC_PV_TRAP and TRC_HVM_IOMEM_READ) have multiple
> + * record formats. These event flags distinguish between the
> + * different formats.
> + */
> +#define TRC_64_FLAG 0x100 /* Addresses are 64 bits (instead of 32 bits) */
>
> /* This structure represents a single trace buffer record. */
> struct t_rec {
> --
> 1.7.2.5
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@xxxxxxxxxxxxx
> http://lists.xen.org/xen-devel
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