[Xen-devel] [PATCH v2] AMD: Enable WC+ memory type on family 10 processors

[Boris Ostrovsky <boris.ostrovsky@xxxxxxx>]

# HG changeset patch
# User Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
# Date 1358452024 18000
# Node ID 40881d58e991fb6bc6089e0dcea23059cf651892
# Parent  b6195e277da52129d5d79f29ccac0e7290643e37
AMD: Enable WC+ memory type on family 10 processors

In some cases BIOS may not enable WC+ memory type on family 10 processors,
instead converting what would be WC+ memory to CD type. On guests using
nested pages this could result in performance degradation. This patch
enables WC+.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxx>

diff -r b6195e277da5 -r 40881d58e991 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c    Wed Jan 16 14:15:44 2013 +0000
+++ b/xen/arch/x86/cpu/amd.c    Thu Jan 17 14:47:04 2013 -0500
@@ -495,6 +495,18 @@ static void __devinit init_amd(struct cp
                set_bit(X86_FEATURE_ARAT, c->x86_capability);
 
        /*
+        * On family 10h BIOS may not have properly enabled WC+ support, causing
+        * it to be converted to CD memtype. This may result in performance
+        * degradation for certain nested-paging guests. Prevent this conversion
+        * by clearing bit 24 in MSR_F10_BU_CFG2.
+        */
+       if (c->x86 == 0x10) {
+               rdmsrl(MSR_F10_BU_CFG2, value);
+               value &= ~(1ULL << 24);
+               wrmsrl(MSR_F10_BU_CFG2, value);
+       }
+
+       /*
         * Prior to Family 0x14, perf counters are not reset during warm reboot.
         * We have to reset them manually.
         */
diff -r b6195e277da5 -r 40881d58e991 xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h   Wed Jan 16 14:15:44 2013 +0000
+++ b/xen/include/asm-x86/msr-index.h   Thu Jan 17 14:47:04 2013 -0500
@@ -220,8 +220,9 @@
 #define MSR_F10_MC4_MISC2              0xc0000409
 #define MSR_F10_MC4_MISC3              0xc000040A
 
-/* AMD Family10h MMU control MSRs */
-#define MSR_F10_BU_CFG                  0xc0011023
+/* AMD Family10h Bus Unit MSRs */
+#define MSR_F10_BU_CFG                 0xc0011023
+#define MSR_F10_BU_CFG2                0xc001102a
 
 /* Other AMD Fam10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058


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