[Xen-devel] [PATCH 13/45] xen: arm64: dcache flush

[Ian Campbell <ian.campbell@xxxxxxxxxx>]

This drops the
    "m" (*_p)
asm contraint. I can't figure out what this was for.

Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
 xen/include/asm-arm/arm32/page.h |    2 ++
 xen/include/asm-arm/arm64/page.h |    2 ++
 xen/include/asm-arm/page.h       |   30 ++++++++++++++----------------
 3 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
index edf324c..dfbf4b0 100644
--- a/xen/include/asm-arm/arm32/page.h
+++ b/xen/include/asm-arm/arm32/page.h
@@ -23,6 +23,8 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
         : : "r" (pte.bits), "r" (p) : "memory");
 }
 
+#define __flush_xen_dcache_one(va) WRITE_CP32((uint32_t) va, DCCMVAC)
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ARM_ARM32_PAGE_H__ */
diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h
index 6053bc2..7b297b5 100644
--- a/xen/include/asm-arm/arm64/page.h
+++ b/xen/include/asm-arm/arm64/page.h
@@ -18,6 +18,8 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
         : : "r" (pte.bits), "r" (p) : "memory");
 }
 
+#define __flush_xen_dcache_one(va) asm volatile ("dc cvac, %0;" : : "r" (va))
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ARM_ARM64_PAGE_H__ */
diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index f1a2fe2..3b6b0f9 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -230,6 +230,14 @@ static inline lpae_t mfn_to_p2m_entry(unsigned long mfn, 
unsigned int mattr)
     return e;
 }
 
+#if defined(CONFIG_ARM_32)
+# include <asm/arm32/page.h>
+#elif defined(CONFIG_ARM_64)
+# include <asm/arm64/page.h>
+#else
+# error "unknown ARM variant"
+#endif
+
 /* Architectural minimum cacheline size is 4 32-bit words. */
 #define MIN_CACHELINE_BYTES 16
 /* Actual cacheline size on the boot CPU. */
@@ -243,7 +251,7 @@ static inline void flush_xen_dcache_va_range(void *p, 
unsigned long size)
     void *end;
     dsb();           /* So the CPU issues all writes to the range */
     for ( end = p + size; p < end; p += cacheline_bytes )
-        WRITE_CP32((uint32_t) p, DCCMVAC);
+        __flush_xen_dcache_one(p);
     dsb();           /* So we know the flushes happen before continuing */
 }
 
@@ -254,15 +262,13 @@ static inline void flush_xen_dcache_va_range(void *p, 
unsigned long size)
     typeof(x) *_p = &(x);                                               \
     if ( sizeof(x) > MIN_CACHELINE_BYTES || sizeof(x) > alignof(x) )    \
         flush_xen_dcache_va_range(_p, sizeof(x));                       \
-    else                                                                \
-        asm volatile (                                                  \
-            "dsb;"   /* Finish all earlier writes */                    \
-            STORE_CP32(0, DCCMVAC)                                      \
-            "dsb;"   /* Finish flush before continuing */               \
-            : : "r" (_p), "m" (*_p));                                   \
+    else {                                                              \
+        dsb();   /* Finish all earlier writes */                        \
+        __flush_xen_dcache_one(_p);                                     \
+        dsb();   /* Finish flush before continuing */                   \
+    }                                                                   \
 } while (0)
 
-
 /*
  * Flush all hypervisor mappings from the TLB and branch predictor.
  * This is needed after changing Xen code mappings.
@@ -385,14 +391,6 @@ static inline int gva_to_ipa(uint32_t va, paddr_t *paddr)
 
 #endif /* __ASSEMBLY__ */
 
-#if defined(CONFIG_ARM_32)
-# include <asm/arm32/page.h>
-#elif defined(CONFIG_ARM_64)
-# include <asm/arm64/page.h>
-#else
-# error "unknown ARM variant"
-#endif
-
 /* These numbers add up to a 39-bit input address space.  The  ARMv7-A
  * architecture actually specifies a 40-bit input address space for the p2m,
  * with an 8K (1024-entry) top-level table. */
-- 
1.7.2.5


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