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[Xen-devel] [PATCH 44/45] xen: arm: Explicitly setup VPIDR & VMPIDR at start of day



These are supposed to reset to the value of the underlying hardware
but appears not to be on at least some v8 models. There's no harm in
setting them explicitly.

Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
 xen/arch/arm/setup.c         |    5 +++++
 xen/include/asm-arm/cpregs.h |    6 ++++++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index cee4478..e867ae7 100644
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -56,6 +56,11 @@ static void __init init_idle_domain(void)
 
 static void __init processor_id(void)
 {
+
+    /* Setup the virtual ID to match the physical */
+    WRITE_SYSREG32(READ_SYSREG32(MIDR_EL1), VPIDR_EL2);
+    WRITE_SYSREG(READ_SYSREG(MPIDR_EL1), VMPIDR_EL2);
+
 #if defined(CONFIG_ARM_64)
     printk("64-bit Processor Features: %016"PRIx64" %016"PRIx64"\n",
            READ_SYSREG64(ID_AA64PFR0_EL1), READ_SYSREG64(ID_AA64PFR1_EL1));
diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h
index 676c8cf..908aad9 100644
--- a/xen/include/asm-arm/cpregs.h
+++ b/xen/include/asm-arm/cpregs.h
@@ -95,6 +95,8 @@
 #define CCSIDR          p15,1,c0,c0,0   /* Cache Size ID Registers */
 #define CLIDR           p15,1,c0,c0,1   /* Cache Level ID Register */
 #define CSSELR          p15,2,c0,c0,0   /* Cache Size Selection Register */
+#define VPIDR           p15,4,c0,c0,0   /* Virtualization Processor ID 
Register */
+#define VMPIDR          p15,4,c0,c0,5   /* Virtualization Multiprocessor ID 
Register */
 
 /* CP15 CR1: System Control Registers */
 #define SCTLR           p15,0,c1,c0,0   /* System Control Register */
@@ -278,6 +280,10 @@
 #define VBAR_EL2                HVBAR
 #define VTCR_EL2                VTCR
 #define VTTBR_EL2               VTTBR
+#define MIDR_EL1                MIDR
+#define VPIDR_EL2               VPIDR
+#define MPIDR_EL1               MPIDR
+#define VMPIDR_EL2              VMPIDR
 
 #endif
 
-- 
1.7.2.5


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