Re: [Xen-devel] [PATCH V2 3/4] arm: allocate per-PCPU domheap pagetable pages

[Tim Deegan <tim@xxxxxxx>]

Hi, 

At 12:21 +0100 on 23 Apr (1366719671), Ian Campbell wrote:
> > > +    /* Change to this CPUs pagetables */
> > > +    flush_xen_text_tlb();
> > > +
> > > +    ttbr = (uintptr_t) virt_to_maddr(this_cpu(xen_pgtable));
> > > +    WRITE_SYSREG64(ttbr, TTBR0_EL2);
> > 
> > isb() here, to make sure the CP write completes? 
> 
> Hrm, we don't have one in the primary CPU bring up either. 
> 
> flush_xen_text_tlb starts with an isb, which I suspect is sufficient? (I
> vaguely remember having a conversation along those lines when this code
> was changed to look like this).

Hrmn.  I guess that does turn out OK, but given that this happens
exactly once per CPU, the extra ISB is a cheap enough price to pay for
making the code obviously correct.

Tim.

> > > +    dsb();                         /* Ensure visibility of HTTBR update 
> > > */
> 
> I think this comment is actually misleading since it doesn't actually
> ensure the visibility, just that things won't cross the boundary.
> 
> I'll try and improve the comment here and in the other site too, does
> ths sound right?:
>         WRITE_SYSREG64(ttbr, TTBR0_EL2);
>         dsb(); /* ensure memory accesses do not cross over the TTBR0 write */
>         /* flush_xen_text_tlb contains an ISB which ensures the
>         TTBR0_EL2 
>          * update has completed. */
>         flush_xen_text_tlb();
> ?
> 
> 
> 
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