[Xen-devel] [PATCH] xen/arm: Implement MPIDR per VCPU

[Julien Grall <julien.grall@xxxxxxxxxx>]

Use different affinity for each VCPU and always expose an SMP systems to
the guest.

Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
 xen/arch/arm/domain.c           |   11 +++++++++--
 xen/include/asm-arm/processor.h |    6 ++++++
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index ff1410d..4654c9b 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -150,7 +150,8 @@ static void ctxt_switch_to(struct vcpu *n)
     isb();
 
     WRITE_SYSREG32(n->domain->arch.vpidr, VPIDR_EL2);
-    WRITE_SYSREG(n->domain->arch.vmpidr, VMPIDR_EL2);
+    WRITE_SYSREG(n->domain->arch.vmpidr | (n->vcpu_id << MPIDR_AFF0_SHIFT),
+                 VMPIDR_EL2);
 
     /* VGIC */
     gic_restore_state(n);
@@ -495,7 +496,13 @@ int arch_domain_create(struct domain *d, unsigned int 
domcr_flags)
 
     /* Default the virtual ID to match the physical */
     d->arch.vpidr = boot_cpu_data.midr.bits;
-    d->arch.vmpidr = boot_cpu_data.mpidr.bits;
+    /*
+     * Expose an SMP systems and remove the AFF0. It will be replace by
+     * the VPCU ID
+     * TODO: handle multi-threading processor
+     */
+    d->arch.vmpidr = boot_cpu_data.mpidr.bits & MPIDR_AFF0_MASK;
+    d->arch.vmpidr = (d->arch.vmpidr & ~MPIDR_UP) | MPIDR_SMP;
 
     /* TODO: retrieve the evtchn IRQ from the guest DTS */
     if ( d->domain_id )
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 1c9d793..5181e7b 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -6,6 +6,12 @@
 /* MIDR Main ID Register */
 #define MIDR_MASK    0xff0ffff0
 
+/* MPIDR Multiprocessor Affinity Register */
+#define MPIDR_UP            (1 << 30)
+#define MPIDR_SMP           (1 << 31)
+#define MPIDR_AFF0_SHIFT    (0)
+#define MPIDR_AFF0_MASK     (0xff << MPIDR_AFF0_SHIFT)
+
 /* TTBCR Translation Table Base Control Register */
 #define TTBCR_EAE    0x80000000
 #define TTBCR_N_MASK 0x07
-- 
1.7.10.4


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