Re: [Xen-devel] [PATCH 03/10] xen: arm: reduce instruction cache and tlb flushes to inner-shareable.

[Tim Deegan <tim@xxxxxxx>]

At 12:19 +0100 on 04 Jul (1372940342), Tim Deegan wrote:
> At 12:07 +0100 on 04 Jul (1372939621), Tim Deegan wrote:
> > At 17:10 +0100 on 28 Jun (1372439449), Ian Campbell wrote:
> > > Now that Xen maps memory and performs pagetable walks as inner shareable 
> > > we
> > > don't need to push updates down so far when modifying page tables etc.
> > > 
> > > Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
> > 
> > > --- a/xen/include/asm-arm/arm32/page.h
> > > +++ b/xen/include/asm-arm/arm32/page.h
> > > @@ -39,8 +39,8 @@ static inline void flush_xen_text_tlb(void)
> > >      asm volatile (
> > >          "isb;"                        /* Ensure synchronization with 
> > > previous changes to text */
> > >          STORE_CP32(0, TLBIALLH)       /* Flush hypervisor TLB */
> > > -        STORE_CP32(0, ICIALLU)        /* Flush I-cache */
> > > -        STORE_CP32(0, BPIALL)         /* Flush branch predictor */
> > > +        STORE_CP32(0, ICIALLUIS)      /* Flush I-cache */
> > > +        STORE_CP32(0, BPIALLIS)       /* Flush branch predictor */
> > >          "dsb;"                        /* Ensure completion of TLB+BP 
> > > flush */
> > >          "isb;"
> > >          : : "r" (r0) /*dummy*/ : "memory");
> > > @@ -54,7 +54,7 @@ static inline void flush_xen_data_tlb(void)
> > >  {
> > >      register unsigned long r0 asm ("r0");
> > >      asm volatile("dsb;" /* Ensure preceding are visible */
> > > -                 STORE_CP32(0, TLBIALLH)
> > > +                 STORE_CP32(0, TLBIALLHIS)
> > >                   "dsb;" /* Ensure completion of the TLB flush */
> > >                   "isb;"
> > >                   : : "r" (r0) /* dummy */: "memory");
> > > @@ -69,7 +69,7 @@ static inline void flush_xen_data_tlb_range_va(unsigned 
> > > long va, unsigned long s
> > >      unsigned long end = va + size;
> > >      dsb(); /* Ensure preceding are visible */
> > >      while ( va < end ) {
> > > -        asm volatile(STORE_CP32(0, TLBIMVAH)
> > > +        asm volatile(STORE_CP32(0, TLBIMVAHIS)
> > >                       : : "r" (va) : "memory");
> > >          va += PAGE_SIZE;
> > >      }
> > 
> > That's OK for actual Xen data mappings, map_domain_page() &c., but now
> > set_fixmap() and clear_fixmap() need to use a stronger flush whenever
> > they map device memory.  The same goes for create_xen_entries() when
> > ai != WRITEALLOC.
> 
> Ian has pointed out that this is actually making the flushes _stronger_
> (and that in general the TLB flush operations need a bit of attention).
> 
> So I suggest that we drop the TLB-flush parts of this patch for now, and
> address that whole area separately.  In the meantime, the cache-flush
> parts are Acked-by: Tim Deegan <tim@xxxxxxx>.

Wait, no - that made no sense. :)  I retract the ack, and let's start
again with the TLB-flush ops.  I don't think anything else in this
series relies on this patch.

Tim.

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