Re: [Xen-devel] [PATCH] Intel/VPMU: Add support for full-width PMC writes

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 05.08.13 at 22:11, Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> wrote:
> On 07/29/2013 05:56 AM, Dietmar Hahn wrote:
>> Am Montag 22 Juli 2013, 14:54:31 schrieb Boris Ostrovsky:
>>> A recent Linux commit (069e0c3c405814778c7475d95b9fff5318f39834) added
>>> support for full-width PMC writes to performance counter registers,
>>> making these registers default for perf. Since current Xen VPMU does
>>> not support these new MSRs perf will fail to initialise in guests.
>>>
>>> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>
>>>
>>> Question to Intel folks: Do we need to update MSR bitmap for both original
>>> (0xc1) and alias (0x4c1) registers or will either one suffice?
> 
> Ping to Intel engineers.

I'm waiting for a response from them too, but ...

> I'll resend this with fixes but I'd like to hear first whether I really 
> need to deal
> with MSR bitmaps. I could test to see how it behaves on my system but I am
> not convinced that even if bitmap uses single bit for both aliases on my 
> HW it
> will be safe to assume that this is the expected behavior on all processors.

... why don't you just assume you need to set both bits unless
proven otherwise, to be on the safe side?

Jan


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